公开(公告)号：EP3309836A1

公开(公告)日：2018-04-18

申请号：EP17162330.9

申请日：2017-03-22

申请人： eMemory Technology Inc.

发明人： TING, Yun-Jen ,  LAI, Chih-Wei ,  SHEN, Chiun-Chi ,  HSU, Hsin-Kun

IPC分类号： H01L27/02

CPC分类号： H02H9/046 ,  G11C17/16 ,  H04L9/3278

摘要： An ESD circuit is connected with a pad. The ESD circuit includes a P-type transistor, an N-type transistor and a control circuit. A first source/drain terminal of the P-type transistor is connected with the pad. A first source/drain terminal of the N-type transistor is connected with a second source/drain terminal of the P-type transistor. A second source/drain terminal of the N-type transistor is connected with a first node. The control circuit is connected with the pad, the first node, a gate terminal of the P-type transistor and a gate terminal of the N-type transistor. When the pad receives an ESD zap, the control circuit provides a first voltage drop to the P-type transistor and provides a second voltage drop to the N-type transistor, so that the P-type transistor and the N-type transistor are turned on.

摘要翻译： ESD电路连接到一个焊盘。 ESD电路包括P型晶体管，N型晶体管和控制电路。 P型晶体管的第一源极/漏极端子与焊盘连接。 N型晶体管的第一源极/漏极端子与P型晶体管的第二源极/漏极端子连接。 N型晶体管的第二源极/漏极端连接第一节点。 控制电路与焊盘，第一节点，P型晶体管的栅极端子和N型晶体管的栅极端子连接。 当所述焊盘接收到ESD消除时，所述控制电路向所述P型晶体管提供第一电压降，并向所述N型晶体管提供第二电压降，以使所述P型晶体管和所述N型晶体管导通 上。