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    COMPUTER IMPLEMENTED METHOD FOR PROCESSING A FRAME SEQUENCE, DIGITAL FRAME PROCESSING DEVICE COMPUTER PROGRAM PRODUCT AND MONITORING SYSTEM
    5.
    发明公开
    COMPUTER IMPLEMENTED METHOD FOR PROCESSING A FRAME SEQUENCE, DIGITAL FRAME PROCESSING DEVICE COMPUTER PROGRAM PRODUCT AND MONITORING SYSTEM 审中-公开

    公开(公告)号：EP3534294A1

    公开(公告)日：2019-09-04

    申请号：EP18159762.6

    申请日：2018-03-02

    申请人： Akademia Gorniczo-Hutnicza im. Stanislawa Staszica w Krakowie

    发明人： Grega, Micha ,  Dziech, Andrzej ,  Rusek, Krzysztof ,  Matiolanski, Andrzej ,  Guzik, Piotr

    IPC分类号： G06K9/00

    摘要： A computer implemented method for processing a frame sequence to generate an alarm when a dangerous object is being used including a frame acquisition (11) step, a division into sub-regions (12) step, object identification (13) step and decision making (14) step, in which alert generation (16) step is executed if decision made in decision making step (14) is positive. Division into sub-regions (12) step includes division of the frame into sub-regions that overlap and have minimal dimension of at least 100 pixels. Object identification step (13) is executed in sub-region by sub-region manner and includes processing a frame with a deep neural network trained to detect the dangerous object and returns probability of detection for sub-regions of the frame formed into probability map corresponding to the frame. Decision made in decision making (14) step is based on at least a first criterion and a second criterion applying to the subsequent frames and corresponding probability maps. The first criterion includes probability of detection within a predefined number N of subsequent frames being above predefined value of p min . The second criterion includes the minimal distance between sub-regions in which probability of detection above predefined value of p min was observed in subsequent frames being lower than given value d max .

    SYSTEM FOR IMPROVING QUALITY OF ELECTRICAL ENERGY
    7.
    发明公开
    SYSTEM FOR IMPROVING QUALITY OF ELECTRICAL ENERGY 审中-公开

    公开(公告)号：EP3402029A1

    公开(公告)日：2018-11-14

    申请号：EP18169609.7

    申请日：2018-04-26

    申请人： Akademia Gorniczo-Hutnicza im. Stanislawa Staszica w Krakowie

    发明人： DZIADECKI, Aleksander ,  GRZEGORSKI, Janusz ,  SKOTNICZNY, Józef

    IPC分类号： H02J3/18 ,  H02J7/34

    CPC分类号： H02J3/1842 ,  H02J7/345

    摘要： A system is composed of an active parallel compensator comprising coupling filters (3,4,5) in each phase conductor (L1, L2, L3) and an AC/DC power electronic converter, and/or a dynamic voltage restorer system comprising in each phase conductor a transformer (Tr1, Tr2, Tr3) and a coupling filter (7, 8, 9) and AC/DC power electronic converters (10, 11, 12) and an energy storage in the form of a storage capacitor (C1) included at DC terminals of said converters (6, 10, 11, 12). In each phase conductor in the LCLR type coupling filters (3, 4, 5; 7, 8, 9) each of resistors is replaced by an energy recovery system composed of a half-bridge system of power electronic switch (16 ,17, 18; 26, 27, 28) connected by means of chokes (D1, D2, D3; D4, D5, D6) and a voltage and current measurement block (13, 14, 15; 23, 24, 25) to the coupling filter in place of a replaced resistor, and signal conductors of the voltage and current measurement block are connected to the switch. In the active parallel compensator circuit, capacitors (C2, C3) connected in series are coupled to both outputs of each of the switches (16, 17, 18) and form an intermediate energy storage, wherein the latter by means of a power electronic converter (22), with an input circuit being galvanically isolated from a DC/DC output circuit, is connected to terminals of a storage capacitor (C1). Common point of the capacitors (C2, C3) is connected to a neutral conductor (N) and by means of the voltage and current measurement blocks (13, 14, 15) to one of the outputs of the coupling filters (3, 4, 5). In the dynamic voltage restorer system circuit, separately for each phase, capacitors in series (C4, C5; C6, C7; C8, C9) are coupled to both outputs of each of the power electronic switches (26, 27, 28) and by means of individual converters (32, 33, 34) they are connected to the storage capacitor (C1). For each phase respectively, common point of the capacitors (C4, C5; C6, C7; C8, C9) is connected by means of the voltage and current measurement block (23, 24, 25) to one of the outputs of the coupling filter (7, 8, 9).