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    SEQUENTIAL MONITORING AND MANAGEMENT OF CODE SEGMENTS FOR RUN-TIME PARALLELIZATION
    1.
    发明公开
    SEQUENTIAL MONITORING AND MANAGEMENT OF CODE SEGMENTS FOR RUN-TIME PARALLELIZATION 审中-公开
    序列监控和代码段的运行时并行化管理

    公开(公告)号：EP3264263A1

    公开(公告)日：2018-01-03

    申请号：EP17170203.8

    申请日：2017-05-09

    申请人： Centipede Semi Ltd.

    发明人： KOREN, Shay ,  PORAT, Arie Hacohen Ben ,  GOREN, Ido ,  MIZRAHI, Noam ,  FRIEDMANN, Jonathan

    IPC分类号： G06F9/38 ,  G06F11/34

    CPC分类号： G06F11/3644 ,  G06F9/30058 ,  G06F9/3808 ,  G06F9/3838 ,  G06F9/3861 ,  G06F11/3466

    摘要： A processor includes an instruction pipeline and control circuitry. The instruction pipeline is configured to process instructions of program code. The control circuitry is configured to monitor the processed instructions at run-time, to construct an invocation data structure comprising multiple entries, wherein each entry (i) specifies an initial instruction that is a target of a branch instruction, (ii) specifies a portion of the program code that follows one or more possible flow-control traces beginning from the initial instruction, and (iii) specifies, for each possible flow-control trace specified in the entry, a next entry that is to be processed following processing of that possible flow-control trace, and to configure the instruction pipeline to process segments of the program code, by continually traversing the entries of the invocation data structure.

    摘要翻译： 处理器包括指令流水线和控制电路。 指令流水线被配置为处理程序代码的指令。 控制电路被配置为在运行时监视处理的指令以构建包括多个条目的调用数据结构，其中每个条目（i）指定作为分支指令的目标的初始指令，（ii）指定部分 从初始指令开始，遵循一个或多个可能的流控制轨迹的程序代码，以及（iii）针对在该项目中指定的每个可能的流控轨迹，指定在处理该项目之后要处理的下一个项目 可能的流程控制跟踪，并通过不断遍历调用数据结构的条目来配置指令流水线来处理程序代码段。

    A METHOD AND A PROCESSOR
    2.
    发明公开
    A METHOD AND A PROCESSOR 审中-公开
    一种方法和一种处理器

    公开(公告)号：EP3306468A1

    公开(公告)日：2018-04-11

    申请号：EP17188441.4

    申请日：2017-08-29

    申请人： Centipede Semi Ltd.

    发明人： FRIEDMANN, Jonathan ,  MIZRAHI, Noam ,  MANDLER, Alberto

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/30043 ,  G06F9/3808 ,  G06F9/3863 ,  G06F9/3867

    摘要： A method includes, in a processor having a pipeline, fetching instructions of program code at run-time, in an order that is different from an order-of-appearance of the instructions in the program code. The instructions are divided into segments having segment identifiers (IDs). An event, which warrants flushing of instructions starting from an instruction belonging to a segment, is detected. In response to the event, at least some of the instructions in the segment that are subsequent to the instruction, and at least some of the instructions in one or more subsequent segments that are subsequent to the segment, are flushed from the pipeline based on the segment IDs.

    摘要翻译： 一种方法包括，在具有流水线的处理器中，按照与程序代码中的指令的出现顺序不同的顺序在运行时获取程序代码的指令。 这些指令被分成具有段标识符（ID）的段。 检测到一个事件，该事件允许从属于一个段的指令开始刷新指令。 响应于该事件，在该指令之后的该段中的至少一些指令以及在该段之后的一个或多个后续段中的至少一些指令中的至少一些指令基于 段ID。

    RUN-TIME CODE PARALLELIZATION WITH CONTINUOUS MONITORING OF REPETITIVE INSTRUCTION SEQUENCES
    3.
    发明公开
    RUN-TIME CODE PARALLELIZATION WITH CONTINUOUS MONITORING OF REPETITIVE INSTRUCTION SEQUENCES 审中-公开
    运行代码并行连续监视重复指令序列

    公开(公告)号：EP3238040A1

    公开(公告)日：2017-11-01

    申请号：EP15872056.5

    申请日：2015-12-09

    申请人： Centipede Semi Ltd.

    发明人： MIZRAHI, Noam ,  MANDLER, Alberto ,  KOREN, Shay ,  FRIEDMANN, Jonathan

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3851 ,  G06F9/381 ,  G06F9/45525 ,  G06F9/46

    摘要： A method includes, in a processor (20) that executes instructions of program code, monitoring instructions of a repetitive sequence of the instructions that traverses a flow-control trace so as to construct a specification of register access by the monitored instructions. Based on the specification, multiple hardware threads are invoked to execute respective segments of the repetitive instruction sequence at least partially in parallel. Monitoring of the instructions continues in at least one of the segments during execution.

    摘要翻译： 一种方法包括：在执行程序代码的指令的处理器（20）中，监视遍历流量控制轨迹的指令的重复序列的指令，以便通过所监视的指令构建寄存器访问的规范。 基于该规范，调用多个硬件线程以至少部分并行地执行重复指令序列的各个段。 监视指令在执行期间至少在一个段中继续。

    PROCESSOR WITH EFFICIENT MEMORY ACCESS
    4.
    发明公开
    PROCESSOR WITH EFFICIENT MEMORY ACCESS 审中-公开
    具有高效存储器访问的处理器

    公开(公告)号：EP3320428A1

    公开(公告)日：2018-05-16

    申请号：EP16820923.7

    申请日：2016-07-04

    申请人： Centipede Semi Ltd.

    发明人： MIZRAHI, Noam ,  FRIEDMANN, Jonathan

    IPC分类号： G06F9/38 ,  G06F9/34

    CPC分类号： G06F9/3832 ,  G06F9/35 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/384

    摘要： A method includes, in a processor (20), processing program code that includes memory- access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory (41) in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory (50) in the processor, based on the identified relationship.

    RUN-TIME CODE PARALLELIZATION USING OUT-OF-ORDER RENAMING WITH PRE-ALLOCATION OF PHYSICAL REGISTERS
    8.
    发明公开
    RUN-TIME CODE PARALLELIZATION USING OUT-OF-ORDER RENAMING WITH PRE-ALLOCATION OF PHYSICAL REGISTERS 审中-公开

    公开(公告)号：EP3368974A1

    公开(公告)日：2018-09-05

    申请号：EP16859154.3

    申请日：2016-08-04

    申请人： Centipede Semi Ltd.

    发明人： TENNENHAUS, Omri ,  MANDLER, Alberto ,  MIZRAHI, Noam

    IPC分类号： G06F9/38

    CPC分类号： G06F9/384 ,  G06F9/3838

    摘要： A method includes processing a sequence of instructions of program code that are specified using one or more architectural registers, by a hardware-implemented pipeline that renames the architectural registers in the instructions so as to produce operations specified using one or more physical registers. At least first and second segments of the sequence of instructions are selected, wherein the second segment occurs later in the sequence than the first segment. One or more of the architectural registers in the instructions of the second segment are renamed, before completing renaming the architectural registers in the instructions of the first segment, by pre-allocating one or more of the physical registers to one or more of the architectural registers.