公开(公告)号：EP4405809A1

公开(公告)日：2024-07-31

申请号：EP22873387.9

申请日：2022-08-23

申请人： Wisconsin Alumni Research Foundation

发明人： SOHI, Gurindar, Singh ,  BAONI, Vanshika ,  MITTAL, Adarsh

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F1/04 ,  G06F12/0873

CPC分类号： Y02D10/00 ,  G06F9/30043 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/35

公开(公告)号：EP3320428A1

公开(公告)日：2018-05-16

申请号：EP16820923.7

申请日：2016-07-04

申请人： Centipede Semi Ltd.

发明人： MIZRAHI, Noam ,  FRIEDMANN, Jonathan

IPC分类号： G06F9/38 ,  G06F9/34

CPC分类号： G06F9/3832 ,  G06F9/35 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/384

摘要： A method includes, in a processor (20), processing program code that includes memory- access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory (41) in terms of one or more register names. A relationship between the memory addresses accessed by two or more of the memory-access instructions is identified, based on respective formats of the memory addresses specified in the symbolic expressions. An outcome of at least one of the memory-access instructions is assigned to be served from an internal memory (50) in the processor, based on the identified relationship.

公开(公告)号：EP3234769A1

公开(公告)日：2017-10-25

申请号：EP15816988.8

申请日：2015-12-02

申请人： Qualcomm Incorporated

发明人： ACHARYA, Anirudh Rajendra

IPC分类号： G06F9/38

CPC分类号： G06F13/24 ,  G06F9/3808 ,  G06F9/3832 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3879 ,  G06F9/461 ,  G06F11/00 ,  G06F12/023 ,  G06F2212/251 ,  G06T1/20

摘要： A command processor may process a command stream for execution by at least one processor, including storing data associated with a first set of one or more operations in the command stream in a trace buffer, wherein the first set of one or more operations accesses one or more memory locations in memory, and wherein the data include an indication of contents of the one or more memory locations associated with the first set of one or more operations. The command processor may interrupt the processing of the command stream. The command processor may, in response to resuming processing of the command stream subsequent to the interrupting of the processing of the command stream, replay at least a portion of the command stream, including processing a second set of one or more operations of the command stream based at least in part on the data stored in the trace buffer.

摘要翻译： 命令处理器可处理用于由至少一个处理器执行的命令流，包括将与命令流中的第一组一个或多个操作相关联的数据存储在跟踪缓冲器中，其中第一组一个或多个操作访问一个或多个操作 存储器中更多的存储器位置，并且其中数据包括与第一组一个或多个操作相关联的一个或多个存储器位置的内容的指示。 命令处理器可能中断命令流的处理。 命令处理器可以响应于在中断命令流的处理之后恢复命令流的处理，重放命令流的至少一部分，包括处理命令流的一个或多个操作的第二集合 至少部分基于存储在跟踪缓冲器中的数据。

公开(公告)号：EP2889759A8

公开(公告)日：2016-02-24

申请号：EP14193268.1

申请日：2014-11-14

申请人： Intel Corporation

发明人： Lee, Victor W.

IPC分类号： G06F9/38

CPC分类号： G06F3/0688 ,  G06F3/0604 ,  G06F3/0638 ,  G06F9/3004 ,  G06F9/30167 ,  G06F9/38 ,  G06F9/3832 ,  G06F13/28 ,  G06F2003/0695

摘要： A processor of an aspect includes an on-die programmable architecturally-visible storage. The processor also includes a decode unit to receive a data access instruction of an instruction set of the processor. The data access instruction to indicate a data address that is to be associated with data to be stored in the on-die programmable architecturally-visible storage, to indicate a data size associated with the data to be stored in the on-die programmable architecturally-visible storage, and to indicate a destination storage location of the processor. An execution unit is coupled with the decode unit and the on-die programmable architecturally-visible storage. The execution unit is on-die with the on-die programmable storage. The execution unit is operable, in response to the data access instruction, to store the data, which is associated with the data address and the data size, in the destination storage location that is to be indicated by the instruction.

摘要翻译： 一个形态的处理器包括接通可编程架构可见存储。 因此处理器包括解码单元，用于接收设置处理器的指令的一个数据访问指令。 该数据访问指令，以指示没有数据地址将要关联的与将要存储在片上的可编程架构可见存储的数据，以指示与所述数据相关联的数据的大小将被存储在片上的可编程architecturally- 可见的存储，并指示所述处理器的目的地存储位置。 的执行单元与所述解码单元和所述接通可编程架构可见存储。 所述执行单元是在与上最可编程存储。 所述执行单元是可操作的，响应于数据访问指令，来存储数据，这一切都与数据地址，并在目的地存储位置中的数据相关联的大小做是由指令来指示。

公开(公告)号：EP2972791A1

公开(公告)日：2016-01-20

申请号：EP14724200.2

申请日：2014-03-14

申请人： Qualcomm Incorporated

发明人： DIEFFENDERFER, James Norris ,  MORROW, Michael William ,  SMITH, Rodney Wayne ,  SCHOTTMILLER, Jeffery M. ,  HIGDON, Daniel S. ,  MCILVAINE, Michael Scott ,  STEMPEL, Brian Michael ,  KOTHARI, Kulin Narendra

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3832 ,  G06F9/30032 ,  G06F9/3828

摘要： A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.

摘要翻译： 处理器，用于根据解码的移动立即指令，其中所述即时是在结构寄存器被移动（拷贝或写）存储在高速缓存中的恒定值（立即或文字）。 恒定值存储在缓存中的项目。 高速缓存中的每个条目都包含一个字段，表示无论其储存的恒定值是有效的，并且场与架构寄存器中的条目相关联。 一旦一个恒定值被存储在缓存中，它可立即转发到处理器管线，其中经解码的指令可能需要恒定值作为操作数。

公开(公告)号：EP2764433A1

公开(公告)日：2014-08-13

申请号：EP12838041.7

申请日：2012-09-24

申请人： International Business Machines Corporation

发明人： GSCHWIND, Michael, Karl ,  SALAPURA, Valentina

IPC分类号： G06F9/34

CPC分类号： G06F9/3834 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30185 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/462

摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs the current operand state information indicating whether corresponding current operands are any one of enabled or disabled for use by a first program module, the first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands, wherein a current operand is accessed by a machine instruction of said first program module, the accessing comprising using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.

公开(公告)号：EP1840735A3

公开(公告)日：2014-04-23

申请号：EP07108697.9

申请日：2000-12-15

申请人： Fujitsu Ltd.

发明人： Miyake, Hideo c/o FUJITSU LIMITED ,  Suga, Atsuhiro c/o FUJITSU LIMITED ,  Nakamura, Yasuki c/o FUJITSU LIMITED

IPC分类号： G06F9/38

CPC分类号： G06F9/3834 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3861

摘要： A processor includes a history control unit (51) that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit (51) overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address. The processor can perform a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations.

公开(公告)号：EP1031919B1

公开(公告)日：2008-10-08

申请号：EP00103800.9

申请日：2000-02-23

申请人： NEC CORPORATION

发明人： Stone, Harold S., NEC Research Institute, Inc. ,  Sakr, Majd F., NEC Research institute Inc. ,  Reinhold, Mark B., NEC Research Institute, Inc.

IPC分类号： G06F9/38

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832

公开(公告)号：EP1644823B1

公开(公告)日：2007-11-21

申请号：EP04753838.4

申请日：2004-06-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： FILIPPO, Michael, A. ,  PICKETT, James, K. ,  SANDER, Benjamin, T. ,  GOPAL, Rama, S.

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/3861

摘要： A microprocessor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler (118). The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C). In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit (126C) is configured to replay at least one of the issued memory operations by providing an indication to the scheduler (118). The scheduler (118) is configured to responsively reissue the memory operations identified by the load store unit (126C).

公开(公告)号：EP1644823A1

公开(公告)日：2006-04-12

申请号：EP04753838.4

申请日：2004-06-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： FILIPPO, Michael, A. ,  PICKETT, James, K. ,  SANDER, Benjamin, T. ,  GOPAL, Rama, S.

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3826 ,  G06F9/3832 ,  G06F9/3834 ,  G06F9/3861

摘要： A microprocessor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler (118). The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C). In response to detection of incorrect data speculation for one of the issued memory operations, the load store unit (126C) is configured to replay at least one of the issued memory operations by providing an indication to the scheduler (118). The scheduler (118) is configured to responsively reissue the memory operations identified by the load store unit (126C).