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    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：EP2660714B1

    公开(公告)日：2018-06-06

    申请号：EP13163470.1

    申请日：2013-04-12

    申请人： Renesas Electronics Corporation

    发明人： Suzuki, Hitoshi ,  Adachi, Koji

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3001 ,  G06F9/3009 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/4881 ,  G06F9/5077 ,  G06F2209/5018

    摘要： A related art semiconductor device suffers from a problem that a processing capacity is decayed by switching an occupied state for each partition. A semiconductor device according to the present invention includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread without depending on the thread schedule as the partition indicated by a first occupation control signal according to a first occupation control signal output when the execution unit executes a first occupation start instruction.

    Configurable data transfer in a digital signal processing system
    7.
    发明授权
    Configurable data transfer in a digital signal processing system 有权
    数字信号处理系统中的可配置数据传输

    公开(公告)号：EP2587384B1

    公开(公告)日：2017-07-12

    申请号：EP12189414.1

    申请日：2012-10-22

    申请人： Imagination Technologies Limited

    发明人： Anderson, Adrian John ,  Wass, Gary Christopher ,  Davies, Gareth John

    IPC分类号： G06F13/28 ,  G06F9/54 ,  G06F15/167 ,  G06F9/38 ,  G06F12/10 ,  G06F9/30 ,  G06F9/50

    CPC分类号： G06F3/0607 ,  G06F3/0629 ,  G06F3/0658 ,  G06F3/0673 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/5016 ,  G06F9/542 ,  G06F9/544 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/251

    摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of hardware peripherals, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the hardware peripherals together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the hardware peripherals and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected hardware peripheral to read data from or write data to the memory device via its memory access channel.

    摘要翻译： 描述了用于在数字信号处理系统中传输数据的技术。 在一个示例中，数字信号处理系统包括多个硬件外围设备，每个硬件外围设备连接到存储器访问控制器并且每个被配置为从存储器设备读取数据，对数据执行一个或多个操作，并且将数据写入到存储器设备 。 为避免将硬件外设硬连线在一起，并提供可配置的数字信号处理系统，多线程处理器控制硬件外设与存储器之间的数据传输。 每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使选定的硬件外设能够从存储器读取数据或向存储器写入数据 设备通过其存储器访问通道。

    MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS
    9.
    发明公开
    MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT MANAGEMENT OF INSTRUCTION ATOMICITY VOLATIONS IN SOFTWARE PROGRAMS AT COMPUTING SYSTEMS 审中-公开
    机构以在计算机系统软件程序，违约ANWEISUNGSATOMIZITÄT动态和高效的管理PERMIT

    公开(公告)号：EP2972878A4

    公开(公告)日：2016-11-09

    申请号：EP13877966

    申请日：2013-03-15

    申请人： INTEL CORP

    发明人： DAUTENHAHN NATHAN ,  GOTTSCHLICH JUSTIN E ,  POKAM GILLES A ,  PEREIRA CRISTIANO L ,  HU SHILIANG ,  DANNE KLAUS ,  KASSA ROLF

    IPC分类号： G06F11/36 ,  G06F9/46 ,  G06F11/14 ,  G06F11/34

    CPC分类号： G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

    摘要： A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

    摘要翻译： 一种机制被描述为软件程序雅鼎用于便利指令原子侵犯的动态，高效的管理。 实施例的方法中，如所描述的，包括接收，在从记录系统中，运行的第一宏指令的第一软件线程的记录，并运行一个第二宏指令的第二软件线程的重放逻辑。 所述第一软件线程与第二软件线程由第一芯和一个第二芯在计算设备处执行的分别，一个处理器。 记录系统可以记录在第一和第二宏指令之间的交错。 该方法包括：正确重放的第一和第二个宏指令间剩余物的记录精确地他们发生。 正确重放可以包括重放的第一和第二宏指令本地内存状态并在第一和第二软件线程的全局内存状态。