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1.发明公开
公开(公告)号：EP1916534A1
公开(公告)日：2008-04-30
申请号：EP06022162.9
申请日：2006-10-23
IPC分类号： G01R31/3181 , G06F17/50
CPC分类号： G01R31/31727 , G01R31/31725 , G06F17/5031 , G06F2217/84
摘要： The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a third step of introducing one or more potential malfunctions of the logic circuit related to the one or more exceptions into the representation of the logic circuit to produce a modified representation of the logic circuit; a fourth step of determining whether functional behaviour of the modified representation of the logic circuit differs from functional behaviour of the first representation of the logic circuit; and a fifth step of reporting a result relating to the difference in the functional behaviour of the modified representation of the logic circuit from the functional behaviour of the initial representation of the logic circuit.
摘要翻译： 本发明涉及一种用于验证逻辑电路中的一个或多个异常的方法，包括以下步骤：提供逻辑电路的初始表示的第一步骤; 指示逻辑电路的至少一个异常的第二步骤; 将与所述一个或多个异常相关的逻辑电路的一个或多个潜在故障引入所述逻辑电路的表示以产生所述逻辑电路的修改表示的第三步骤; 确定逻辑电路的修改表示的功能行为与逻辑电路的第一表示的功能行为不同的第四步骤; 以及第五步骤，将与逻辑电路的修改表示的功能行为的差异与逻辑电路的初始表示的功能行为相关的结果报告。
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公开(公告)号：EP1221663A3
公开(公告)日：2006-04-05
申请号：EP01108653.5
申请日：2001-04-05
发明人： Johannsen, Peer
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： The present invention relates to a method of circuit verification in digital design and in particular relates to a method of register transfer level property checking to enable the same. Today's electrical circuit designs frequently contain up to several million transistors and circuit designs need to be checked to ensure that circuits operate correctly. Formal methods for verification are becoming increasingly attractive since they confirm design behaviour without exhaustively simulating a design. The present invention provides a digital circuit design verification method wherein, prior to a property checking process for each property of a non-reduced RTL model, a reduced RTL model is determined, which reduced RTL model retains specific signal properties of a non-reduced RTL model which are to be checked. A linear signal width reduction causes an exponential reduction of the induced state space. Reducing state space sizes in general goes hand in hand with reduced verification runtimes, and thus speeding up verification tasks.
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公开(公告)号：EP2797017B1
公开(公告)日：2020-04-01
申请号：EP14166051.4
申请日：2014-04-25
发明人： Straßer, Dominik , Niesler, Gerrit , Fit, Mirko , Brinkmann, Raik
IPC分类号： G06F17/50
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公开(公告)号：EP2088521A1
公开(公告)日：2009-08-12
申请号：EP08002479.7
申请日：2008-02-11
发明人： Beyer, Sven , Schönherr, Jens , Bormann, Jörg
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method for verifying at least one aspects of a digital circuit, the method comprising: providing a set of operations to be performed by the digital circuit, each one of the set of operations having at least one functional element; identifying a first subset of a plurality of the at least one functional element; describing in a description the plurality of the at least one functional element of the identified first subset in terms of properties, each one of the properties having an assumption component and a proof component; formally verifying each one of the properties; arranging the plurality of the at least one functional element of the identified first subset to be proven for the digital circuit in an arrangement with temporal relations satisfying at least said description; analysing completeness of the arrangement of the plurality of the at least one functional element to verify that the at least one aspects of the digital circuit are completely verified.
摘要翻译： 1。一种用于验证数字电路的至少一个方面的方法，所述方法包括：提供将由所述数字电路执行的一组操作，所述一组操作中的每一个具有至少一个功能元件; 识别多个所述至少一个功能元件的第一子集; 在描述中在特性方面描述所识别的第一子集的多个所述至少一个功能元件，所述特性中的每一个具有假设部件和证明部件; 正式验证每一个属性; 将所识别的第一子集的所述至少一个功能元件的所述多个功能元件布置成具有满足至少所述描述的时间关系的布置; 分析所述多个所述至少一个功能元件的布置的完整性以验证所述数字电路的所述至少一个方面被完全验证。
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5.发明公开Equivalence verification between transaction level models and RTL examples of processors 审中-公开Äquivalenzüberprüfungzwischen Transaktionsebenenmodellen und RTL-Beispielen von Prozessoren
公开(公告)号：EP1933245A1
公开(公告)日：2008-06-18
申请号：EP06026768.9
申请日：2006-12-22
发明人： Bormann, Jörg , Beyer, Sven , Skalberg, Sebastian
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A method for formally verifying the equivalence of an architecture description with an implementation description is disclosed. The method comprises:
- reading an implementation description;
- reading an architecture description;
- demonstrating that during execution of a same program with same initial values an architecture sequence of data transfers described by the architecture description is mappable to an implementation sequence of data transfers implemented by the implementation description, such that the mapping is bijective and ensures that the temporal order of the architecture sequence of data transfers corresponds to the temporal order of the implementation sequence of data transfers;
- outputting a result of the verification of the equivalence of the architecture description with the implementation description.摘要翻译： 公开了一种用于正式验证体系结构描述与实现描述的等价性的方法。 该方法包括： - 读取实现描述; - 阅读建筑描述; - 表明在执行具有相同初始值的相同程序期间，由架构描述描述的架构数据传输序列可映射到由实现描述实现的数据传输的实现序列，使得映射是双射的并且确保时间 数据传输的架构序列的顺序对应于数据传输的实现顺序的时间顺序; - 输出结构描述的等同性的验证结果与实现描述。
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公开(公告)号：EP2546767B1
公开(公告)日：2014-12-31
申请号：EP11173498.4
申请日：2011-07-11
发明人： Brinkmann, Raik
IPC分类号： G06F17/50
CPC分类号： G06F17/504
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公开(公告)号：EP1916534B1
公开(公告)日：2009-12-16
申请号：EP06022162.9
申请日：2006-10-23
IPC分类号： G01R31/3181 , G06F17/50
CPC分类号： G01R31/31727 , G01R31/31725 , G06F17/5031 , G06F2217/84
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公开(公告)号：EP1221663B1
公开(公告)日：2009-06-24
申请号：EP01108653.5
申请日：2001-04-05
发明人： Johannsen, Peer
IPC分类号： G06F17/50
CPC分类号： G06F17/504
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公开(公告)号：EP3474196A1
公开(公告)日：2019-04-24
申请号：EP18202161.8
申请日：2018-10-23
发明人： Rafaila, Monica
摘要： The present invention proposes a computer implemented method of selecting a prover among a plurality of provers for a design to be verified. The method comprises collecting, by a data module, raw data relating to the design, and extracting from the raw data a plurality of input features, transforming, by a transformer module, the plurality of input features, wherein transforming the plurality of features comprises applying a linear regression to the plurality of features, classifying using a classification module, the provers from the plurality of provers, in which the classification module is adapted to predict a best prover being the prover which solves a property faster than the remaining provers of the plurality of provers, selecting one or more provers based on the results of the classification.
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10.发明公开Cloud-based digital verification system and method 审中-公开Verfahren und System zur Cloud-basierten digitalen Verifikation
公开(公告)号：EP2797017A1
公开(公告)日：2014-10-29
申请号：EP14166051.4
申请日：2014-04-25
发明人： Straßer, Dominik , Niesler, Gerrit , Fit, Mirko , Brinkmann, Raik
IPC分类号： G06F17/50
摘要： A method for formal verification of a digital circuit using a cloud-based verification engine. The method comprises extracting a proof problem from a design of a digital circuit with a local processor, reducing said proof problem to proof relevant data, encrypting said reduced proof problem, transmitting said encrypted reduced proof problem to a remote server, decrypting said encrypted reduced proof problem at said remote server, storing said reduced proof problem in a memory at said remote server, running a proof on said reduced proof problem at said remote server to generate a proof result; encrypting said proof result at said remote server; transmitting said encrypted proof result to said local processor; decrypting said encrypted proof result at said local processor; and reconstructing a verification result of said digital circuit design at said local processor using said decrypted proof result.
摘要翻译： 一种使用基于云的验证引擎对数字电路进行形式验证的方法。 该方法包括：利用本地处理器从数字电路的设计中提取证明问题，减少所述证明问题以证明相关数据，加密所述减少验证问题，将所述加密的减少验证问题发送给远程服务器，解密所述加密的减少证明 在所述远程服务器上存储所述减少验证问题到所述远程服务器的存储器中，对所述远程服务器上的所述减少验证问题进行证明，以生成验证结果; 在所述远程服务器上加密所述验证结果; 将所述加密验证结果发送到所述本地处理器; 在所述本地处理器处解密所述加密验证结果; 以及使用所述解密证明结果在所述本地处理器处重构所述数字电路设计的验证结果。
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