公开(公告)号：EP1857925A2

公开(公告)日：2007-11-21

申请号：EP07251933.3

申请日：2007-05-10

申请人： Intel Corporation

发明人： Cornea-Hasegan, Marius

IPC分类号： G06F7/491

CPC分类号： G06F7/4915 ,  G06F2207/4911

摘要： According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

摘要翻译： 。根据在本申请中游离缺失的主题的盘的实施例中，浮点小数的乘法和/或十进制定点乘法可以使用现有的硬件为二进制数的操作来实现。 实现可以在软件中进行，硬件，或者软件和硬件的结合。 预先计算的常数并是近似值为10负幂和以二进制格式存储可用于通过与乘以结果四舍五入相乘结果到指定的精度预先计算的常数。 此外，可以是十进制乘法的几个部分可以并行进行。 进一步，可以用于检测中点和精确确定具有恒定的，而不是昂贵的剩余计算的简单比较。

公开(公告)号：EP0055124B1

公开(公告)日：1990-01-31

申请号：EP81306018.3

申请日：1981-12-22

申请人： Bull HN Information Systems Inc.

发明人： Negi, Virendra S. ,  Tague, Steven A.

IPC分类号： G06F7/52

CPC分类号： G06F7/4915

公开(公告)号：EP1857925A3

公开(公告)日：2008-12-10

申请号：EP07251933.3

申请日：2007-05-10

申请人： Intel Corporation

发明人： Cornea-Hasegan, Marius

IPC分类号： G06F7/491

CPC分类号： G06F7/4915 ,  G06F2207/4911

摘要： According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

公开(公告)号：EP1831782A2

公开(公告)日：2007-09-12

申请号：EP04748730.1

申请日：2004-07-12

申请人： Kilic, Halil

发明人： Kilic, Halil

IPC分类号： G06F7/60

CPC分类号： G06F7/4915 ,  G06F7/4833 ,  G06F7/496 ,  G06F7/60 ,  G06F2207/49195

摘要： The present invention describes a new computer architecture. A digital processor comprises processing units which comprise decoders for decoding a first part of the N- bit data word into digital code with only one bit high. These bits are processed in arithmetic modules, which receive outputs from two processing units, and an activation signal produced by an instruction circuit. The instruction circuit receives knowledge on the data to be processed by reading the second part of the N-bit data words. This second part may be divided into several so-called DNA groups. The DNA group contain information on the type of symbols/values of the data to be processed. Using this knowledge on the data, very fast and simple parallel processing can be executed.

公开(公告)号：EP1857925B1

公开(公告)日：2011-10-26

申请号：EP07251933.3

申请日：2007-05-10

申请人： Intel Corporation

发明人： Cornea-Hasegan, Marius

IPC分类号： G06F7/491

CPC分类号： G06F7/4915 ,  G06F2207/4911

公开(公告)号：EP0686911A1

公开(公告)日：1995-12-13

申请号：EP95303670.4

申请日：1995-05-30

申请人： ADVANCED MICRO DEVICES INC.

发明人： Mondul, Donald D. ,  Asghar, Safdar M.

IPC分类号： G06F7/49 ,  G06F7/52 ,  G06F1/03

CPC分类号： G06F7/5306 ,  G06F1/03 ,  G06F7/49 ,  G06F7/4915 ,  G06F7/523 ,  G06F7/5235 ,  G06F7/5324 ,  G06F2207/3816

摘要： A method and apparatus are disclosed for determining the product of N numbers in base Z. The method comprises the steps of: (1) providing a first and succeeding storage arrays. The first storage array includes storage loci containing indicia of products of a first digit and a second digit. A first pointer is positioned by the first digit, a second pointer is positioned by the second digit, and the pointers cooperate to identify a first solution locus containing a first product. Succeeding storage arrays are associated with succeeding N numbers. The first and second pointers identify a subset of storage loci in a succeeding storage array. A third pointer associated with a third digit identifies a second solution locus among the subset. Each array's pointers cooperate to designate a next-succeeding array and a subset of storage loci, and each next-succeeding array has a pointer associated with a next digit to designate a next solution locus until N numbers are involved in the product. Each succeeding array stores indicia of the product of the digit of the number associated with that array and the product identified by the preceding array; (2) determining a partial product for each combination of the digits of each of the N numbers, each partial product having a combinational significance established by the significance of each digit involved; (3) accumulating partial products in hierarchically arranged cells according to a particular relationship; and (4) effecting a shifting accumulation operation among the cells.

摘要翻译： 公开了一种用于确定基座Z中N个数的乘积的方法和装置。该方法包括以下步骤：（1）提供第一和后续存储阵列。 第一存储阵列包括包含第一数字和第二数字的产品的标记的存储轨迹。 第一指针由第一数字定位，第二指针由第二数位置，并且指针协作以识别包含第一乘积的第一解轨迹。 成功的存储阵列与后续N个数字相关联。 第一个和第二个指针在后续的存储阵列中标识一个存储轨迹的子集。 与第三数字相关联的第三指针识别子集中的第二解轨迹。 每个阵列的指针协作以指定下一个后续阵列和存储轨迹的子集，并且每个下一个后续阵列具有与下一个数字相关联的指针，以指定下一个解决方案轨迹，直到产生N个数字。 每个后续阵列存储与该阵列相关联的数字的数字和由前一个阵列识别的乘积的乘积的标记; （2）确定每个N个数字的数字的每个组合的部分积，每个部分乘积具有由所涉及的每个数字的重要性确定的组合意义; （3）根据特定的关系在分层布置的单元中累积部分乘积; 和（4）在单元之间进行移位累积操作。

公开(公告)号：EP0055124A1

公开(公告)日：1982-06-30

申请号：EP81306018.3

申请日：1981-12-22

申请人： Bull HN Information Systems Inc.

发明人： Negi, Virendra S. ,  Tague, Steven A.

IPC分类号： G06F7/52

CPC分类号： G06F7/4915

摘要： A decimal multiplier operates serially by digit. Each multiplier digit is selected in turn, and a PROM is used to generate the product of the selected multiplier digit with each mutliplicand digit in turn, the products being added into a partial product. Each product is generated in two successive cycles, as a units digit in a units cycle followed by a tens digit in a tens cycle. Thus a conventional single- digit decimal adder is used. Further, there are two carry flip-flops, a units carry flip-flop and a tens carry fli-flop, each being operative only during its respective cycles and holding any carry over through the intervening cycle. Means are provided for skipping a multiplicand cycle if a multiplier digit is 0.

摘要翻译： 十进制乘法器以数字顺序运行。 依次选择每个乘数，并且使用PROM依次生成所选乘法器数乘积的乘积，产品被添加到部分乘积中。 每个产品在两个连续循环中生成，作为单位周期中的单位数字，后跟十位数十位。 因此使用常规的singledigit十进制加法器。 此外，有两个进位触发器，单元进位触发器和十进位触发器，每个只在其各自的周期期间操作，并且通过中间周期保持任何进位。 如果乘数为0，则提供用于跳过被乘数循环的装置。