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公开(公告)号：EP1936809B1
公开(公告)日：2012-03-07
申请号：EP07021556.1
申请日：2007-11-06
申请人： Altera Corporation
IPC分类号： H03K19/173
CPC分类号： G06F7/52 , G06F7/5324
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公开(公告)号：EP1936809A3
公开(公告)日：2010-12-01
申请号：EP07021556.1
申请日：2007-11-06
申请人： Altera Corporation
IPC分类号： H03K19/173
CPC分类号： G06F7/52 , G06F7/5324
摘要： A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks.
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公开(公告)号：EP1752870B1
公开(公告)日：2008-12-31
申请号：EP06118102.0
申请日：1994-09-02
发明人： Nishiyama, Tamotsu Matsushita Elect. Ind. Co., Ltd , Tsubata Shintaro Matsushita Elect. Ind. Co., Ltd
IPC分类号： G06F7/533
CPC分类号： G06F7/53 , G06F7/4824 , G06F7/52 , G06F7/533 , G06F17/5045
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公开(公告)号：EP1475699B1
公开(公告)日：2008-11-12
申请号：EP04018295.8
申请日：1994-09-02
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/4824 , G06F7/52 , G06F7/533 , G06F17/5045
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公开(公告)号：EP1752870A3
公开(公告)日：2007-05-16
申请号：EP06118102.0
申请日：1994-09-02
发明人： Nishiyama, Tamotsu Matsushita Elect. Ind. Co., Ltd , Tsubata Shintaro Matsushita Elect. Ind. Co., Ltd
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/4824 , G06F7/52 , G06F7/533 , G06F17/5045
摘要： With respect to each bit of a multiplier factor, it is judged whether or not the multiplicand is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.
摘要翻译： 关于乘数的每一位，判断被乘数是变数还是常数。 如果乘数是常数，则判断乘数的关注位是否具有值1.只有在乘数的关注位为1时，才生成用于输出的电路，如 部分产品，表示被乘数的信号。 然后将指示被乘数的信号移位一位，以使得到的信号被重新设置为指示被乘数的信号。 通过对乘数的所有位重复执行上述处理，生成用于计算乘法因子的各位的部分乘积的电路。
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公开(公告)号：EP1475699A2
公开(公告)日：2004-11-10
申请号：EP04018295.8
申请日：1994-09-02
IPC分类号： G06F7/52
CPC分类号： G06F7/53 , G06F7/4824 , G06F7/52 , G06F7/533 , G06F17/5045
摘要： A multiplier for outputting the product of a multiplier factor A=A1-A2, where A1 and A2 are constants, and a multiplicand X, comprising a first partial-product generator receiving A1 and X and outputting partial products only with respect to the bits having the value of 1 in A1; a second partial-product generator receiving A2 and X and outputting partial products only with respect to the bits having the value of 1 in A2; a logic NOT means receiving the output signals from said second partial-product generator and outputting the logic NOT signals thereof; and a partial-product-sum means for receiving the output signals from said first partial-product generator, the output signals from said logic NOT means, and a correction signal, calculating the sum thereof, and outputting the sum as the product of the multiplier factor A and the multiplicand X.
摘要翻译： 用于输出乘数A = A1-A2的乘法器，其中A1和A2是常数，乘法器X包括接收A1和X的第一部分乘积生成器，并且仅相对于具有 A1中的值为1; 接收A2和X的第二部分积发生器，并且仅在A2中相对于具有值1的位输出部分乘积; 逻辑不意味着从所述第二部分积发生器接收输出信号并输出其逻辑非信号; 以及部分积和装置，用于从所述第一部分积发生器接收输出信号，从所述逻辑非装置输出信号和校正信号，计算其总和，并输出该和作为乘数的乘积 因子A和被乘数X.
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8.发明公开Method and apparatus for automatically designing a multiplier circuit 失效Verfahren und Vorrichtung zum automatischen Entwurf einer Multiplikatorschaltung。
公开(公告)号：EP0642093A3
公开(公告)日：1996-03-13
申请号：EP94113808.3
申请日：1994-09-02
CPC分类号： G06F7/53 , G06F7/4824 , G06F7/52 , G06F7/533 , G06F17/5045
摘要： With respect to each bit of a multiplier factor, it is judged whether or not the multiplicand is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.
摘要翻译： 用于输出乘数A = A1-A2的乘法器，其中A1和A2是常数，乘法器X包括接收A1和X的第一部分乘积生成器，并且仅相对于具有 A1中的值为1; 接收A2和X的第二部分积发生器，并且仅在A2中相对于具有值1的位输出部分乘积; 逻辑不意味着从所述第二部分积发生器接收输出信号并输出其逻辑非信号; 以及部分积和装置，用于从所述第一部分积发生器接收输出信号，从所述逻辑非装置输出信号和校正信号，计算其总和，并输出该和作为乘数的乘积 因子A和被乘数X.
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9.发明公开Method and apparatus for automatically designing a multiplier circuit 失效方法，系统和设备，用于乘法器电路的自动设计，并通过进行该处理乘法器电路
公开(公告)号：EP0642093A2
公开(公告)日：1995-03-08
申请号：EP94113808.3
申请日：1994-09-02
CPC分类号： G06F7/53 , G06F7/4824 , G06F7/52 , G06F7/533 , G06F17/5045
摘要： With respect to each bit of a multiplier factor, it is judged whether or not the multiplicand is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.
摘要翻译： 相对于一乘数的每个位，则判断被乘数是否是一个变量或常数。 如果乘数为常数时，判断一个位在乘数关注是否具有值1。只有当在乘数关注的位1，生成用于输出铃声的电路，如 一个部分乘积，表示被乘数的信号。 表示被乘数的信号由一个位，因此没有得到的信号设定为新表示被乘数的信号开始偏移。 通过相对于反复执行上述过程的乘数的所有位中，生成用于计算部分乘积相对于乘数的每个位的电路。
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10.发明公开
公开(公告)号：EP2849305A1
公开(公告)日：2015-03-18
申请号：EP14184923.2
申请日：2014-09-16
发明人： Naoi, Shinya , Noro, Yasuhiro , Miyazaki, Yasuyuki , Shimoo, Takahiro , Asano, Toshiaki , Miyaji, Hideyuki , Yurino, Shinji , Watanabe, Yuji
摘要： According to an embodiment, a voltage fluctuation suppressing apparatus is provided with a power storage device connected to an electric power system, a basic control unit to control an output of the power storage device, a voltage detector to measure a voltage of a connection point to the electric power system, and an output control unit to divide a control amount to be outputted to the basic control unit into a reactive power command value and an active power command value and to output them. The output control unit is provided with a reactive power upper limit value calculation unit, a reactive power calculation/output unit, and an active power calculation/output unit. The active power calculation/output unit outputs 0 as the active power command value, when an absolute value of the control value to be outputted to the basic control unit is not more than an absolute value of an upper limit value of the reactive power command value, and outputs a value that is calculated from a prescribed expression and is not 0 as the active power command value, when the absolute value of the control value exceeds the relevant absolute value.
摘要翻译： 根据实施例，电压波动抑制装置具有与电力系统连接的蓄电装置，控制蓄电装置的输出的基本控制单元，电压检测器，测量连接点 电力系统和输出控制单元，将要输出到基本控制单元的控制量分成无功功率指令值和有功功率指令值，并输出。 输出控制单元设置有无功功率上限值计算单元，无功功率计算/输出单元和有功功率计算/输出单元。 有功功率计算/输出单元输出0作为有功功率指令值，当输出到基本控制单元的控制值的绝对值不大于无功功率指令值的上限值的绝对值 ，并且当控制值的绝对值超过相关绝对值时，输出从规定表达式计算出的值，并且不为0作为有功功率指令值。
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