利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

482 records (took 0.013 seconds)

    STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF STORAGE DEVICE
    1.
    发明公开
    STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND OPERATING METHOD OF STORAGE DEVICE 审中-实审

    公开(公告)号：EP4332971A3

    公开(公告)日：2024-05-15

    申请号：EP23193980.2

    申请日：2023-08-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： MUN, Kui-Yon ,  HWANG, Jooyoung ,  KIM, Gyeongmin ,  PARK, Keunsan ,  BAE, Joon-Whan

    IPC: G11C16/04 ,  G06F3/06 ,  G06F12/02 ,  G11C16/10

    CPC classification number: G06F12/0246 ,  G11C16/0425 ,  G11C16/102 ,  G11C2211/564120130101 ,  G06F3/0679

    Abstract: A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells, wherein the controller is further configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device based on a request received from an external host device, select two or more erase units from among a plurality of erase units included in the plurality of memory cells to be allocated to each of the plurality of zones based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones, wherein the nonvolatile memory device includes a plurality of memory chips, wherein each memory chip of the plurality of memory chips includes a plurality of memory blocks, wherein each memory block of the plurality of memory blocks includes at least two erase units, and wherein the controller is further configured to select at least one erase unit from the each memory block to be allocated to a zone.

    FLASH MEMORY REWRITING ARCHITECTURE HAVING NO EXTERNAL LATCH
    4.
    发明公开
    FLASH MEMORY REWRITING ARCHITECTURE HAVING NO EXTERNAL LATCH 审中-公开
    FLASH SPEICHER UMSCHREIBEN ARCHITEKTUR OHNE EXTERNEN LATCH

    公开(公告)号：EP3076395A1

    公开(公告)日：2016-10-05

    申请号：EP16020062.2

    申请日：1999-03-25

    Applicant: LEXAR MEDIA, INC.

    Inventor： Estakhri, Petro

    IPC: G11C16/10

    CPC classification number: G11C16/105 ,  G11C16/102 ,  G11C16/20

    Abstract: A method of operating a memory device includes receiving a read command at command/control logic (240) that is internal to a memory device (200) from an external controller (135) that is external to the memory device; receiving a first address for a used location in a flash array (205) at an address latch (265) from the external controller after receiving the read command at the command/control logic, where the flash array and the address latch are internal to the memory device; reading data from the used location to an internal latch (210) that is internal to the memory device in response to receiving the read command and the first address; indicating to the external controller that reading the data from the used location to the internal latch is ended; receiving a write command from the external controller at the command/control logic after indicating to the external controller that reading the data from the used location to the internal latch is ended; receiving a second address for an unused location in the flash array from the external controller at the address latch after receiving the write command at the command/control logic; and writing the data from the internal latch to the unused location in response to receiving the write command and the second address.

    Abstract translation: 一种操作存储器件的方法包括：从存储器件外部的外部控制器（135）接收位于存储器件（200）内部的命令/控制逻辑（240）处的读命令; 在命令/控制逻辑上接收到读命令之后，从外部控制器在地址锁存器（265）处的闪存阵列（205）中的使用位置的第一地址接收，其中闪存阵列和地址锁存器位于 存储设备; 响应于接收到所述读取命令和所述第一地址，将数据从所述使用位置读取到位于所述存储器设备内部的内部锁存器（210）; 向外部控制器指示从使用位置向内部锁存器读取数据结束; 在向外部控制器指示从所使用的位置到内部锁存器的数据的读取结束之后，以指令/控制逻辑从外部控制器接收写命令; 在命令/控制逻辑上接收到写入命令之后，从地址锁存器的外部控制器接收闪存阵列中的未使用位置的第二地址; 以及响应于接收到所述写命令和所述第二地址，将所述数据从所述内部锁存器写入所述未使用位置。

    ERASE MANAGEMENT IN MEMORY SYSTEMS
    5.
    发明公开
    ERASE MANAGEMENT IN MEMORY SYSTEMS 审中-公开
    LÖSCHVERWALTUNG在SPEICHERSYSTEMEN

    公开(公告)号：EP3022740A1

    公开(公告)日：2016-05-25

    申请号：EP14827142.2

    申请日：2014-07-16

    Applicant: Intel Corporation

    Inventor： WAKCHAURE, Yogesh B. ,  PELSTER, David J. ,  GUO, Xin

    IPC: G11C16/14 ,  G11C16/06

    CPC classification number: G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495

    Abstract: Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system.

    Abstract translation: 计算机处理器硬件接收存储在非易失性存储器系统中的存储单元区域中的数据存储无效数据的通知。 响应于该通知，计算机处理器硬件将该区域标记为存储无效数据。 计算机处理器硬件控制与用替换数据重写存储单元中的无效数据相关联的擦除驻留时间的大小（即，一个或多个单元被设置为擦除状态的时间量）。 例如，为了重新编程相应的存储单元，数据管理器必须擦除存储单元，然后用替换数据对存储单元进行编程。 数据管理逻辑可以将擦除停留时间控制为小于阈值时间值以增强非易失性存储器系统的寿命。

    MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE
    8.
    发明公开
    MULTIPLE PROGRAMMING OF FLASH MEMORY WITHOUT ERASE 审中-公开
    多种编程闪存，但不删除

    公开(公告)号：EP2559036A1

    公开(公告)日：2013-02-20

    申请号：EP11721364.5

    申请日：2011-04-14

    Applicant: Ramot at Tel-Aviv University Ltd.

    Inventor： SHARON, Eran ,  ALROD, Idan ,  LITSYN, Simon ,  ILANI, Ishai

    IPC: G11C16/10 ,  G11C16/34 ,  G11C11/56

    CPC classification number: G11C16/102 ,  G06F12/02 ,  G11C11/5628 ,  G11C16/349

    Abstract: To store, successively, in a plurality of memory cells, first and second pluralities of input bits that are equal in number, a first transformation transforms the first input bits into a first plurality of transformed bits. A first portion of the cells is programmed to store the first transformed bits according to a mapping of bit sequences to cell levels, but, if the first transformation has a variable output length, only if there are few enough first transformed bits to fit in the first cell portion. Then, without erasing a second cell portion that includes the first portion, if respective levels of the cells of the second portion, that represent a second plurality of transformed bits obtained by a second transformation of the second input bits, according to the mapping, are accessible from the current cell levels, the second portion is so programmed to store the second transformed bits.

    Communication adapter for a home appliance
    10.
    发明公开
    Communication adapter for a home appliance 审中-公开
    家用电器的通信适配器

    公开(公告)号：EP2242208A3

    公开(公告)日：2012-10-03

    申请号：EP10001907.4

    申请日：2003-10-01

    Applicant: Mitsubishi Electric Corporation

    Inventor： Higuma, Toshiyasu ,  Kushiro, Noriyuki ,  Ito, Yoshiaki ,  Ochiai, Yoshiko ,  Koizumi, Yoshiaki

    IPC: H04L12/28 ,  G11C16/10 ,  H01H35/00

    CPC classification number: H04L12/282 ,  G11C16/102 ,  H04L12/2825 ,  H04L12/2827 ,  H04L2012/285

    Abstract: The present invention relates to a communication adapter apparatus that connects electrical apparatuses, sensors, and other apparatuses to a network..In order to obtain a communication adapter apparatus that is capable of realizing simplification of setting at the time of execution of works, simplification of execution of works, reduction of power consumption, and simplification of system setting, the communication adapter apparatus according to the invention is a communication adapter that connects one of plural connection object apparatuses having an apparatus object consisting of information, which is based on functions of the apparatuses, and operable control items, respectively and a network to which a controller for remotely controlling the connection object apparatus is connected, the communication adapter including: communication control means that controls transmission and reception of data to and from the network; apparatus communication managing means that copies and saves the apparatus object, saves a procedure for a communication service of the communication control means, and makes it possible to use the connection object apparatus from the network using these saved data; and apparatus interface means that is defined by standards common to all the apparatuses in order to make all the plural communication object apparatuses connectable.

    Abstract translation: 通信适配器装置技术领域本发明涉及将电气设备，传感器等装置与网络连接的通信适配器装置。为了获得能够实现作业执行时的设定简单化的通信适配器装置， 执行作品，降低功耗和简化系统设置，根据本发明的通信适配器装置是通信适配器，其连接具有由信息组成的装置对象的多个连接对象装置中的一个，该装置对象基于 设备和可操作的控制项目，以及连接有用于远程控制所述连接对象设备的控制器的网络，所述通信适配器包括：通信控制装置，其控制向所述网络发送数据和从所述网络接收数据; 设备通信管理装置，其复制并保存设备对象，保存通信控制装置的通信服务的过程，并使得可以使用这些保存的数据从网络使用连接对象装置; 以及为了使所有多个通信对象设备可连接，由所有设备共同的标准定义的设备接口装置。

Patent Agency Ranking