公开(公告)号：EP2408107B1

公开(公告)日：2017-03-08

申请号：EP11005683.5

申请日：2011-07-12

申请人： Eaton Corporation

发明人： Nowak, Michael P. ,  Dimino, Steven A.

IPC分类号： H03H17/02 ,  H03H21/00

CPC分类号： H03H21/0021 ,  H03H17/0289 ,  H03H2021/0049 ,  H03H2021/007 ,  H03H2021/0098

公开(公告)号：EP2408107A3

公开(公告)日：2015-05-27

申请号：EP11005683.5

申请日：2011-07-12

申请人： Eaton Corporation

发明人： Nowak, Michael P. ,  Dimino, Steven A.

IPC分类号： H03H17/02 ,  H03H21/00

CPC分类号： H03H21/0021 ,  H03H17/0289 ,  H03H2021/0049 ,  H03H2021/007 ,  H03H2021/0098

摘要： A system (40) includes a first powered apparatus (42) having a first analog signal (16) with a fundamental frequency (ω o ); and a second apparatus (44) providing load diagnostics or power quality assessment of the first apparatus (42) from a second digital signal (I F (n)). The second apparatus (44) includes an input (46) of the first analog signal, an output (48) of the second digital signal (I F (n)), a processor (22), an adaptive filter (50) executed by the processor, a digital-to-analog converter (20), and an analog-to-digital converter (10). The adaptive filter routine outputs a third digital signal (y(n)) as a function of the second digital signal (I F (n)) and plural adaptive weights (4,6). The digital-to-analog converter inputs the third digital signal (y(n)) and outputs a fourth analog signal (I o est(t)) representative of an estimate of a fundamental frequency component (I o (t)) of the first analog signal (16). The analog-to-digital converter inputs a difference (I(t) - I o est(t)) between the first and the fourth analog signals (I o est(t)), and outputs the second digital signal (I F (n)) representative of the first analog signal with the fundamental frequency component removed.

公开(公告)号：EP2408107A2

公开(公告)日：2012-01-18

申请号：EP11005683.5

申请日：2011-07-12

申请人： Eaton Corporation

发明人： Nowak, Michael P. ,  Dimino, Steven A.

IPC分类号： H03H17/02 ,  H03H21/00

CPC分类号： H03H21/0021 ,  H03H17/0289 ,  H03H2021/0049 ,  H03H2021/007 ,  H03H2021/0098

摘要： A system (40) includes a first powered apparatus (42) having a first analog signal (16) with a fundamental frequency (ω o ); and a second apparatus (44) providing load diagnostics or power quality assessment of the first apparatus (42) from a second digital signal (I F (n)). The second apparatus (44) includes an input (46) of the first analog signal, an output (48) of the second digital signal (I F (n)), a processor (22), an adaptive filter (50) executed by the processor, a digital-to-analog converter (20), and an analog-to-digital converter (10). The adaptive filter routine outputs a third digital signal (y(n)) as a function of the second digital signal (I F (n)) and plural adaptive weights (4,6). The digital-to-analog converter inputs the third digital signal (y(n)) and outputs a fourth analog signal (I o est(t)) representative of an estimate of a fundamental frequency component (I o (t)) of the first analog signal (16). The analog-to-digital converter inputs a difference (I(t) - I o est(t)) between the first and the fourth analog signals (I o est(t)), and outputs the second digital signal (I F (n)) representative of the first analog signal with the fundamental frequency component removed.

公开(公告)号：EP3147777A1

公开(公告)日：2017-03-29

申请号：EP16184520.1

申请日：2016-08-17

申请人： Intel Corporation

发明人： SHEIKH, Farhana ,  LEE, Ching-En ,  XUE, Feng ,  VAIDYA, Anuja S. ,  ALBAN, Eduardo X. ,  ANDERSSON, Albert Oskar Filip ,  CHEN, Chia-Hsiang ,  YEH, Shu-Ping

IPC分类号： G06F9/38

CPC分类号： H03H21/0012 ,  G06F9/3877 ,  G06F17/16 ,  H03H2021/0049 ,  H03H2021/0094 ,  H03H2218/06 ,  H04B1/525

摘要： An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data. In addition, the hardware accelerator unit comprises a convergence detector unit configured to determine a convergence parameter; and a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter. The iteration signal communicates to the calculation unit and the adaptation core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the adaptation core unit.

摘要翻译： 适配硬件加速器包括被配置为以一个或多个预定时间间隔接收多个输入的计算单元，其中每个时间间隔对应于计算迭代，所述多个输入与多个自适应滤波器相关联，每个自适应滤波器具有多个 抽头，并且基于给定的计算迭代确定相关数据和互相关数据。 相关数据包括包括多个子矩阵的相关矩阵，其中确定相关矩阵包括仅确定相关矩阵的上三角形部分和对角线部分中的子矩阵。 此外，适配硬件加速器包括：适配核心单元，被配置为通过利用相关数据和互相关数据，分别基于优化的基于RLS的自适应算法来确定与所述多个自适应滤波器相关联的多个自适应权重。 另外，硬件加速器单元包括：收敛检测器单元，被配置为确定收敛参数; 以及控制器，被配置为基于所述收敛参数为所述预定时间间隔中的每一个生成迭代信号。 迭代信号与计算单元和适配核心单元通信以继续下一个计算迭代或者得出结论，其中结论指示由适配核心单元确定多个自适应权重的最终值。

公开(公告)号：EP1279226A2

公开(公告)日：2003-01-29

申请号：EP01928451.2

申请日：2001-04-19

申请人： Virata Corporation ,  Pal, Debajyoti

发明人： PAL, Debajyoti ,  SLOCK, Dirk

IPC分类号： H03H21/00

CPC分类号： H03H21/0043 ,  H03H2021/0049

摘要： The present invention, generally speaking, accelerates convergence of a fast RLS adaptation algorithm by, following processing of a burst of data, performing postprocessing to remove the effects of prewindowing, fictitious data initialization, or both. This postprocessing is part of a burst mode adaptation strategy in which data (signals) get processed in chunks (bursts). Such a burst mode processing approach is applicable whenever the continuous adaptation of the filter is not possible (algorithmic complexity too high to run in real time) or not required (optimal filter setting varies only slowly with time). Postprocessing consists of a series of 'downdating' operations (as opposed to updating) that in effect advance the beginning point of the data window. The beginning point is advanced beyond fictitious data used for initialization and beyond a prewindowing region. In other variations, downdating is applied to data within a prewindowing region only. The forgetting factor of conventional algorithms can be eliminated entirely. Performance equivalent to that of GWC RLS algorithms is achieved at substantially lower computational cost. In particular, a postprocessing Fast Kalman Algorithm in effect transforms an initialized/prewindowed least squares estimate into a Covariance Window least squares estimate. Various further refinements are possible. Initialization may be cancelled completely or only partially. For example, in order to reduce the dynamic range of algorithmic quantities, it may be advantageous to, in a subsequent initialization, add an increment to a forward error energy quantity calculated during a previous burst. Postprocessing may then be performed to cancel only the added increment. Also, to reduce the usual large startup error transient, the desired response data can be modified in a way that dampens the error transient. The modified desired response data are saved for use in later postprocessing. Furthermore, to allow for more rapid adaptation without the use of an exponential forgetting factor, a weighting factor less than one may be applied to the forward error energy quantity during initialization from one burst to the next. This allows for the most efficient use of data but limited adaptation within a burst, but more rapid adaptation from one burst to the next.