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    LAYERED BAND PASS FILTER
    5.
    发明公开
    LAYERED BAND PASS FILTER 审中-公开
    分层带通滤波器

    公开(公告)号：EP2009787A4

    公开(公告)日：2011-04-13

    申请号：EP07738541

    申请日：2007-03-14

    Applicant: MURATA MANUFACTURING CO

    Inventor： TANIGUCHI TETSUO

    IPC: H03H7/075 ,  H03H7/09

    CPC classification number: H03H7/09 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1775 ,  H03H2001/0085

    Abstract: A capacitance is formed between a ground electrode (109) disposed on a ground electrode forming layer (101) and each of capacitor electrodes (111) to (115) formed on a capacitor electrode forming layer (102). A plurality of inductor electrodes are formed by via electrodes (131) to (140) and the line electrodes (116) to (120). Planes of loops of the plurality of inductor electrodes partially overlap with each other when viewed in a direction in which the inductor electrodes are arranged. In addition, the direction of the loop of the inductor electrode of an LC parallel resonator on an input side (in a first stage) is opposite to the direction of the loop of the inductor electrode of a second-stage LC parallel resonator adjacent to the inductor electrode of the LC parallel resonator on the input side. The direction of the loop of the inductor electrode of an LC parallel resonator on an output side (in a fifth stage) is opposite to the direction of the loop of the inductor electrode of a fourth-stage LC parallel resonator adjacent to the inductor electrode of the LC parallel resonator on the output side.

    NOISE SUPPRESSING CIRCUIT
    6.
    发明公开
    NOISE SUPPRESSING CIRCUIT 审中-公开
    RAUSCHUNTERDRÜCKUNGSSCHALTUNG

    公开(公告)号：EP1783900A1

    公开(公告)日：2007-05-09

    申请号：EP05770436.3

    申请日：2005-08-09

    Applicant: TDK Corporation

    Inventor： Saitoh, Yoshihiro c/o TDK Corporation ,  Ishibashi, Mitsuru c/o TDK Corporation

    IPC: H03H7/09 ,  H04B3/56

    CPC classification number: H03H7/427 ,  H03H7/09 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1758 ,  H04B3/56 ,  H04B2203/5425 ,  H04B2203/547 ,  H04B2203/5483 ,  H04B2203/5491

    Abstract: The present invention realizes a noise suppression circuit capable of suppressing noise in a wide frequency range even if impedance fluctuates on the input side or the output side. A noise suppression circuit has first and second inductors (L1, L2) inserted in series in a first conductive line (3), and a series circuit (15) configured to have a third inductor (L3) and a first capacitor (C1) connected in series. The third inductor (L3) side is connected between the first and second inductors (L1, L2). The noise suppression circuit further includes a second capacitor (C2) whose one end is connected to the first conductive line (3) on the first inductor (L1) side and whose other end is connected between the third inductor and the first capacitor in the series circuit (15).

    Abstract translation: 本发明实现了即使阻抗在输入侧或输出侧波动也能够在宽的频率范围内抑制噪声的噪声抑制电路。 噪声抑制电路具有串联插入第一导线（3）中的第一和第二电感器（L1，L2），并且串联电路（15）被配置为具有连接有第三电感器（L3）和第一电容器（C1） 串联。 第三电感器（L3）侧连接在第一和第二电感器（L1，L2）之间。 噪声抑制电路还包括第二电容器（C2），其一端连接到第一电感器（L1）侧的第一导线（3），并且其另一端连接在第三电感器和串联的第一电容器之间 电路（15）。

    COMMON MODE SIGNAL SUPPRESSING CIRCUIT AND NORMAL MODE SIGNAL SUPPRESSING CIRCUIT
    7.
    发明公开
    COMMON MODE SIGNAL SUPPRESSING CIRCUIT AND NORMAL MODE SIGNAL SUPPRESSING CIRCUIT 审中-公开
    GLEICHTAKTSIGNALUNTERDRÜCKUNGSSCHALTUNGUND NORMALMODUS-SIGNALUNTERDRÜCKUNGSSCHALTUNG

    公开(公告)号：EP1553699A1

    公开(公告)日：2005-07-13

    申请号：EP03788073.9

    申请日：2003-08-11

    Applicant: TDK Corporation

    Inventor： WASAKI, Masaru TDK Corporation ,  SAITOH, Yoshihiro TDK Corporation

    IPC: H03H7/09

    CPC classification number: H03H7/427 ,  H03H7/09 ,  H03H7/1725 ,  H03H7/1758 ,  H03H7/1791 ,  H04B3/28

    Abstract: A common mode signal suppressing circuit comprises: a first winding (11) inserted to a conductor line (3); a second winding (12) that is inserted to a conductor line (4) and coupled to the first winding (11) through a magnetic core (10) and that suppresses common mode signals in cooperation with the first winding (11); and a third winding (13) coupled to the first and second windings (11, 12) through the core (10). The common mode signal suppressing circuit further comprises a phase-inverted signal transmitting circuit (15) connected to the third winding (13) and to the conductor lines (3, 4). The phase-inverted signal transmitting circuit (15) detects a common mode signal on the conductor lines (3, 4), and supplies a phase-inverted signal to the third winding (13), the phase-inverted signal having a phase opposite to the phase of the common mode signal.

    Abstract translation: 共模信号抑制电路包括：插入导线（3）的第一绕组（11）; 第二绕组（12），其插入到导线（4）中并通过磁芯（10）耦合到第一绕组（11），并与第一绕组（11）配合抑制共模信号; 以及通过所述芯（10）耦合到所述第一和第二绕组（11,12）的第三绕组（13）。 共模信号抑制电路还包括连接到第三绕组（13）和导体线（3,4）的相位反转信号发送电路（15）。 相位反转信号发送电路（15）检测导线（3,4）上的共模信号，并向第三绕组（13）提供相位反相信号，相位反相信号具有与 共模信号的相位。

    Schaltungsanordnung zur Filterung eines Hochfequenzsignals
    8.
    发明公开
    Schaltungsanordnung zur Filterung eines Hochfequenzsignals 有权
    用于过滤高频信号的电路装置

    公开(公告)号：EP1128552A1

    公开(公告)日：2001-08-29

    申请号：EP00103653.2

    申请日：2000-02-21

    Applicant: Infineon Technologies AG

    Inventor： Krug, Erwin

    IPC: H03H7/12 ,  H03J3/08

    CPC classification number: H03H7/12 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/175 ,  H03J3/08

    Abstract: Eine Schaltung zur Filterung eines Hochfrequenzsignals, insbesondere in Tunern für Fernsehgeräte, umfaßt einen VCO (6) sowie Tracking-Filter (2, 3, 4), deren Filterbereich von einem Stellsignal (C0) verschiebbar ist. Zum Feinabgleich von Fertigungstoleranzen wird den Filtern (2, 3, 4) ein Korrektursignal (Cl, C2, C3) zugeführt, das am frequenzveränderbaren Element des Filters (2, 3, 4) an dem im Vergleich zum Steuersignal (C0) anderen Pol angelegt wird. Der Wertebereich der Korrektursignale (C1, C2, C3) ist auf den Korrekturbereich beschränkt und ist wesentlich geringer als der Wertebereich für das Stellsignal (C0).

    Abstract translation: 一种用于在调谐器的电视机滤波的高频信号，特别地，包括VCO（6）和跟踪滤波器电路（2，3，4），控制信号（C0）的过滤面积是可移动的。 用于滤波器的制造公差的微调（2，3，4）被提供给一个校正信号（CL，C2，C3），其适用于在所述过滤器（2，3，4）的频率可变元件相比于控制信号（C0）其它极 是。 校正信号（C1，C2，C3）的值的范围被限制在校正区域，并且比用于将控制信号（C0）值的范围低得多。

    A multilayer hybrid circuit
    9.
    发明公开
    A multilayer hybrid circuit 失效
    多层混合电路

    公开(公告)号：EP0433176A3

    公开(公告)日：1992-12-30

    申请号：EP90403576.3

    申请日：1990-12-13

    Applicant: TDK Corporation

    Inventor： Takaya, Minoru ,  Mochizuki, Yoshinori ,  Yasuda, Katsuharu

    IPC: H01L27/01 ,  H01L49/00

    CPC classification number: H03H7/09 ,  H01L27/013 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1758 ,  H03H7/1766 ,  H03H2001/0085 ,  H05K1/16

    Abstract: A multilayer hybrid circuit having a laminated body having at least one of a plurality of dielectric layers, dielectric magnetic layers, and conductive patterns on said dielectric layers and said magnetic layers, is produced through printing process and sintering process, and composes capacitors, inductors, and resistors. An external connection is effected by side terminals positioned on side walls of the laminated body. A coupling conductor which is perpendicular to a dielectric plane is provided for coupling elements on different planes. Said coupling conductor is a succession of essentially S-shaped conductor chips or lines with the ends connected to adjacent conductor chips on different planes. That coupling conductor functions via a through hole conductor in a prior printed circuit board, and has high operational reliability in a component which is produced through sintering process. In one embodiment, an inductor is produced by a pair of coils connected in series with each other to reduce the thickness of the laminated body while providing high inductance.

    A multilayer hybrid circuit
    10.
    发明公开
    A multilayer hybrid circuit 失效
    Mehrschicht-Hybridschaltkreis。

    公开(公告)号：EP0433176A2

    公开(公告)日：1991-06-19

    申请号：EP90403576.3

    申请日：1990-12-13

    Applicant: TDK Corporation

    Inventor： Takaya, Minoru ,  Mochizuki, Yoshinori ,  Yasuda, Katsuharu

    IPC: H01L27/01 ,  H01L49/00

    CPC classification number: H03H7/09 ,  H01L27/013 ,  H03H7/1708 ,  H03H7/1725 ,  H03H7/1758 ,  H03H7/1766 ,  H03H2001/0085 ,  H05K1/16

    Abstract: A multilayer hybrid circuit having a laminated body having at least one of a plurality of dielectric layers, dielectric magnetic layers, and conductive patterns on said dielectric layers and said magnetic layers, is produced through printing process and sintering process, and composes capacitors, inductors, and resistors. An external connection is effected by side terminals positioned on side walls of the laminated body. A coupling conductor which is perpendicular to a dielectric plane is provided for coupling elements on different planes. Said coupling conductor is a succession of essentially S-shaped conductor chips or lines with the ends connected to adjacent conductor chips on different planes. That coupling conductor functions via a through hole conductor in a prior printed circuit board, and has high operational reliability in a component which is produced through sintering process. In one embodiment, an inductor is produced by a pair of coils connected in series with each other to reduce the thickness of the laminated body while providing high inductance.

    Abstract translation: 通过印刷工艺和烧结工艺制造具有层压体的多层混合电路，其具有在所述介电层和所述磁性层上的多个电介质层，电介质磁性层和导电图案中的至少一个的叠层体，并且构成电容器，电感器， 和电阻。 外部连接由位于层叠体的侧壁上的侧端子实现。 提供垂直于电介质平面的耦合导体用于在不同平面上耦合元件。 所述耦合导体是连续的基本上S形的导体芯片或线，其端部连接到不同平面上的相邻导体芯片。 该耦合导体通过现有印刷电路板中的通孔导体起作用，并且在通过烧结工艺制造的部件中具有高操作可靠性。 在一个实施例中，电感器由彼此串联连接的一对线圈产生，以减小层叠体的厚度，同时提供高电感。

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