摘要:
A method of approximate max-log-a-posteriori decoding soft input information related to a transmitted word of a linear block code ( n , k ) and providing hard or soft output information is disclosed. The method comprises the steps of forming a reliability vector from the input information, identifying ( n-k ) linearly independent least reliable symbols and k most reliable symbols, converting a parity check matrix of the linear block code to a pseudo-systematic form with respect to the least reliable symbols, calculating extrinsic information and composite information for the most reliable symbols using the soft input information and the pseudo-systematic parity check matrix, and calculating extrinsic information for the least reliable systems using composite information for the most reliable symbols.
摘要:
In accordance with the invention, the electric signal contains signal information and information which is redundant in respect of the signal information, determined from the signal information. A reliability measure is approximated on the basis of the electric signal in order to form at least one signal value which is determined in accordance with the reliability measure. To this end, a target function containing a model of a transmission canal is optimized (step 101) and the approximation takes place by means of the target function (step 102).
摘要:
Les bits émis sont codés selon le produit d'au moins deux codes en blocs systématiques. Un décodage itératif est appliqué pour déterminer, à chaque étape de recherche de mots de code, une matrice de données ((R)) et une matrice de décision ((D}) utilisées pour l'étape suivante. La nouvelle matrice de décision est déterminée à chaque étape en décodant les lignes ou les colonnes de la matrice d'entrée, et la nouvelle matrice de données est déterminée en prenant en compte des termes de correction qui augmentent la fiabilité du décodage à chaque itération. Les circuits de codage et de décodage (17) sont rendus programmables par une technique de poinçonnage permettant de choisir le nombre de bits transmis par bloc codé, les bits poinçonnés ayant de préférence des positions uniformément distribuées suivant chaque dimension des matrices.
摘要:
The embodiments of the invention disclose a method for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result. The embodiments of the invention also disclose a device for decoding an RS code. By using the invention, the decoding performance of the RS code can be efficiently improved, and the decoding complexity can be reduced.
摘要:
A method and apparatus for layered decoding of a codeword encoded using a Low Density Parity-check code. The code defines a plurality of variable nodes corresponding to the bits of the codeword and a plurality of check nodes. Each check node is associated with two or more variable nodes. The method comprises: defining (510) a plurality of layers, each layer comprising a group of nodes of one type to be updated together; detecting (520) a conflict within a layer, wherein first and second nodes among the group of nodes are associated with a third node of the other type, whereby, in an update-step of the decoding method, both the first and second nodes will attempt to write to a memory address corresponding to the third node; and repeating the update-step, to avoid the conflict, comprising: performing a first update-step (530, 540, 550) wherein the second node updates the third node; and performing a second update-step (560, 570, 580) wherein the first node updates the third node.