公开(公告)号：EP2058781B1

公开(公告)日：2018-05-02

申请号：EP07806207.2

申请日：2007-08-29

申请人： Sony Corporation

发明人： SHIRAI, Taizo ,  SHIBUTANI, Kyoji ,  AKISHITA, Toru ,  MORIAI, Shiho

IPC分类号： G09C1/00 ,  H04L9/06

CPC分类号： H04L9/0625 ,  G09C1/00 ,  H04L9/002 ,  H04L9/0631 ,  H04L2209/122 ,  H04L2209/125

摘要： A common-key blockcipher processing configuration with enhanced immunity against attacks such as saturation attacks and algebraic attacks (XSL attacks) is realized. In an encryption processing apparatus that performs common-key blockcipher processing, S-boxes serving as non-linear transformation processing parts set in round-function executing parts are configured using at least two different types of S-boxes. With this configuration, the immunity against saturation attacks can be enhanced. Also, types of S-boxes present a mixture of different types. With this configuration, the immunity against algebraic attacks (XSL attacks) can be enhanced, thereby realizing a highly secure encryption processing apparatus.

公开(公告)号：EP2015505A3

公开(公告)日：2016-11-16

申请号：EP08012447.2

申请日：2008-07-10

申请人： STMicroelectronics Srl ,  STMicroelectronics, Inc.

发明人： Bertoni, Guido Marco ,  Owen, Jefferson Eugene

IPC分类号： H04L9/06 ,  G09C1/00

CPC分类号： H04L9/0637 ,  G09C1/00 ,  H04L2209/122 ,  H04L2209/125

摘要： An encoding/decoding apparatus comprises a central processing unit and an encryption/decryption accelerator coupled to the central processing unit The accelerator comprises an input for input data to be encrypted/decrypted, an arithmetic logic unit coupled to said input for performing selectable operations on data obtained from said input data and an output for encrypted/decrypted data coupled to said arithmetic logic unit.

公开(公告)号：EP3038288A4

公开(公告)日：2016-08-17

申请号：EP14844770

申请日：2014-05-04

申请人： BLOOMBASE TECHNOLOGIES LIMITED

发明人： BLOOMBASE TECHNOLOGIES LIMITED

IPC分类号： H04L9/06 ,  G09C1/00

CPC分类号： H04L9/0637 ,  G09C1/00 ,  H04L2209/122

公开(公告)号：EP3032523A4

公开(公告)日：2016-08-10

申请号：EP15776988

申请日：2015-02-04

申请人： FUJI ELECTRIC CO LTD

发明人： TAKATSUKASA KENJI

IPC分类号： G09C1/00 ,  G06F7/00 ,  H04L9/06

CPC分类号： H04L9/0637 ,  G09C1/00 ,  H04L9/0631 ,  H04L9/0643 ,  H04L9/3236 ,  H04L9/3239 ,  H04L2209/122

摘要： OBJECT To provide an information processing apparatus, a program and a storage medium capable of performing an efficient computation of a GHASH function. MEANS OF SOLUTION An information processing apparatus has an encryption part that encrypts by block encryption, and is embeddable in an electronic apparatus, and achieves the above object by segmenting an authentication target message into one or more blocks for every 128 bits, the authentication target message including at least a predetermined authentication parameter and first encryption information that is obtained by encrypting plaintext information by the encryption part, successively computing each of the one or more segmented blocks by a GHASH function including a predetermined algorithm, using a plurality of 8-bit arrays including 16 elements, and generating second encryption information that is obtained by encrypting a computed result by the encryption part, to generate an authentication tag.

公开(公告)号：EP3032523A1

公开(公告)日：2016-06-15

申请号：EP15776988.6

申请日：2015-02-04

申请人： Fuji Electric Co., Ltd.

发明人： TAKATSUKASA, Kenji

IPC分类号： G09C1/00 ,  H04L9/32

CPC分类号： H04L9/0637 ,  G09C1/00 ,  H04L9/0631 ,  H04L9/0643 ,  H04L9/3236 ,  H04L9/3239 ,  H04L2209/122

摘要： OBJECT
To provide an information processing apparatus, a program and a storage medium capable of performing an efficient computation of a GHASH function.
MEANS OF SOLUTION
An information processing apparatus has an encryption part that encrypts by block encryption, and is embeddable in an electronic apparatus, and achieves the above object by segmenting an authentication target message into one or more blocks for every 128 bits, the authentication target message including at least a predetermined authentication parameter and first encryption information that is obtained by encrypting plaintext information by the encryption part, successively computing each of the one or more segmented blocks by a GHASH function including a predetermined algorithm, using a plurality of 8-bit arrays including 16 elements, and generating second encryption information that is obtained by encrypting a computed result by the encryption part, to generate an authentication tag.

摘要翻译： 对象提供能够执行GHASH功能的有效计算的信息处理装置，程序和存储介质。 解决方案的方案信息处理装置具有通过块加密进行加密并且可嵌入电子装置的加密部分，并且通过将认证目标消息分割成每128位的一个或多个块来实现上述目的，认证目标消息 包括至少预定的认证参数和通过加密部分加密明文信息而获得的第一加密信息，使用多个8位阵列连续地计算包括预定算法的GHASH功能中的每一个分段块 包括16个元素，并且生成通过加密由加密部分计算的结果加密而获得的第二加密信息，以生成认证标签。

公开(公告)号：EP2863577A1

公开(公告)日：2015-04-22

申请号：EP13807455.4

申请日：2013-06-09

申请人： China Iwncomm Co., Ltd.

发明人： LI, Zhiyong ,  CAO, Jun ,  YAN, Xiang

IPC分类号： H04L9/06

CPC分类号： H04L9/0631 ,  G09C1/00 ,  H04L9/065 ,  H04L9/16 ,  H04L9/3263 ,  H04L2209/122

摘要： Disclosed are a method for conducting data encryption and decryption using a symmetric cryptography algorithm and a table look-up device. The method comprises: when it is determined that it is required to use S-boxes to look up a table in a symmetric cryptography algorithm, determining all types of S-boxes to be used; for each type of S-box, determining the total number N i of the type of S-box, and when N i is larger than 1, determining that the type of S-box meets a multiplexing condition; and when data encryption and decryption are conducted using the symmetric cryptography algorithm, multiplexing at least one type of S-box which meets the multiplexing condition. The present application can reduce the occupation by the symmetric cryptography algorithm of hardware resources under the condition of comparative shortage of hardware resources.

摘要翻译： 本发明公开了用于进行数据加密，并使用对称加密算法和查表装置解密的方法。 该方法包括：当确定开采却是使用S盒查找表的对称加密算法所需的信息，确定开采中使用的所有类型的S盒; 对于每种类型的S-box的，确定性的采矿总数S盒的类型为N i和当N i是大于1的，确定性的挖掘做了S盒的类型满足复用条件; 并且当数据加密和解密使用对称加密算法，复用至少一种类型的S-box这满足复用条件的被进行。 本申请可以硬件资源的短缺比较的条件下，通过减少硬件资源的对称加密算法的占用。

公开(公告)号：EP2237246A4

公开(公告)日：2014-12-31

申请号：EP08702793

申请日：2008-01-18

申请人： FUJITSU LTD

发明人： YAJIMA JUN ,  YAMAMOTO DAI ,  ITOH KOUICHI

IPC分类号： G09C1/00 ,  H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/122 ,  H04L2209/24 ,  H04L2209/805

摘要： When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.

公开(公告)号：EP2575286A1

公开(公告)日：2013-04-03

申请号：EP12185644.7

申请日：2012-09-24

申请人： Kabushiki Kaisha Toshiba

发明人： Kawabata, Takeshi

IPC分类号： H04L9/00 ,  H04L9/06

CPC分类号： H04L9/003 ,  H04L9/0631 ,  H04L2209/04 ,  H04L2209/08 ,  H04L2209/122

摘要： According to an embodiment, an encryption processing apparatus includes a data retaining unit(11) configured to retain data to be processed; a mask retaining unit(21) configured to retain mask data; a first linear transformation unit(B') configured to perform a linear transformation from the mask data to first mask data; a second linear transformation unit(C) configured to perform a linear transformation from the mask data to second mask data; a first calculator(19) configured to calculate first data based upon the data to be processed retained in the data retaining unit and the first mask data; a selecting unit(31) configured to select either one of the first data and the second mask data; a non-linear transformation unit(A) configured to perform a non-linear transformation on the first data or the second mask data selected by the selecting unit; a second calculator(20) configured to calculate second data based upon the first data on which the non-linear transformation is performed by the non-linear transformation unit, and the mask data retained in the mask retaining unit; and a third linear transformation unit(B) configured to perform a linear transformation on the second data. The second data on which the linear transformation is performed by the third linear transformation unit is retained in the data retaining unit as new data to be processed. The second mask data on which the non-linear transformation is performed by the non-linear transformation unit is retained in the mask retaining unit as new mask data.

摘要翻译： 根据实施例，一种加密处理装置包括配置为保留要处理的数据的数据保留单元（11） 配置为保持掩模数据的掩模保持单元（21）; 被配置为执行从所述掩模数据到第一掩模数据的线性变换的第一线性变换单元（B'）; 被配置为执行从掩模数据到第二掩模数据的线性变换的第二线性变换单元（C）; 第一计算器（19），其被配置为基于保留在所述数据保持单元中的待处理数据和所述第一掩码数据来计算第一数据; 被配置为选择所述第一数据和所述第二掩模数据中的任一个的选择单元（31） 被配置为对由选择单元选择的第一数据或第二掩模数据执行非线性变换的非线性变换单元（A） 第二计算器（20），被配置为基于由非线性变换单元执行非线性变换的第一数据和保留在掩模保持单元中的掩码数据来计算第二数据; 以及第三线性变换单元（B），被配置为对所述第二数据执行线性变换。 由第三线性变换单元执行线性变换的第二数据作为要处理的新数据保留在数据保持单元中。 由非线性变换单元执行非线性变换的第二掩模数据作为新的掩模数据保留在掩模保持单元中。

公开(公告)号：EP2209251A3

公开(公告)日：2012-02-22

申请号：EP09176232.8

申请日：2009-11-17

申请人： FUJITSU LIMITED

发明人： Yamamoto, Dai ,  Itoh, Kouichi

IPC分类号： H04L9/06

CPC分类号： H04L9/0625 ,  H04L2209/122

摘要： A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL -1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.

公开(公告)号：EP1975908A1

公开(公告)日：2008-10-01

申请号：EP07706356.8

申请日：2007-01-04

申请人： Sony Corporation

发明人： SHIRAI, Taizo ,  SHIBUTANI, Kyoji

IPC分类号： G09C1/00 ,  H04L9/06

CPC分类号： H04L9/002 ,  H04L9/0625 ,  H04L2209/122

摘要： It is possible to realize a Feistel-type common key block encryption/decryption processing configuration capable of reducing data stored in a memory at a low cost. The Feistel-type common key block encryption/decryption processing repeatedly executes an SP-type F function having nonlinear and linear transform sections by several rounds. At least one of the nonlinear and linear transform processes executed in the F function in each round is executed as a transform process identical with a transform process applied to an encryption/decryption algorithm other than a Feistel-type common key block encryption/decryption algorithm and/or another hash function such as AES and Whirlpool. With this configuration, it is possible to reduce the design cost and the amount of data stored in a memory.

摘要翻译： 可以实现能够以低成本减少存储在存储器中的数据的Feistel型公共密钥块加密/解密处理配置。 Feistel型公共密钥块加密/解密处理重复执行具有非线性和线性变换部分的SP型F函数几轮。 执行在每一轮中的F函数中执行的非线性和线性变换处理中的至少一个作为与应用于除了Feistel型公共密钥块加密/解密算法之外的加密/解密算法的变换处理相同的变换处理， /或另一个散列函数，如AES和Whirlpool。 利用这种配置，可以降低存储在存储器中的设计成本和数据量。