DIODE MODULATOR GENERATING A LINE S-CORRECTION
    1.
    发明授权
    DIODE MODULATOR GENERATING A LINE S-CORRECTION 失效
    二极管调制器用于产生LINE-S校正

    公开(公告)号:EP0870398B1

    公开(公告)日:2004-11-03

    申请号:EP97925242.6

    申请日:1997-06-25

    IPC分类号: H04N3/23

    CPC分类号: H04N3/27 H04N3/237

    摘要: The invention provides a diode modulator circuit which is adapted to supply an acceptable S-correction of the S-linearity error of the line scanning of a picture tube (CRT) at substantially different line scan widths. A known diode modulator comprises two loops. The first loop comprises a series arrangement of a line deflection coil (LD) and an S-capacitor (CS), which series arrangement is arranged in parallel with a first flyback capacitor (CF1) and a first diode (D1). The second loop comprises a modulator coil (LB) arranged in parallel with a second flyback capacitor (CF2) and a second diode (D2). The two loops are arranged in series. An inner-pincushion capacitor (CSM) is arranged in a common path in which the line deflection current (Id) and a modulator current (Ib) flowing through the modulator coil (LB) flow in opposite directions. The amount of S-correction depends on the values of the S-correction capacitor (SC) and the inner-pincushion capacitor (CSM). The S-capacitor (CS) has been omitted in the diode modulator according to the invention. In this way, the amount of S-correction at minimal scan width will be zero because the common current (Im) flowing in the common path is zero if the diode modulator is in equilibrium. The diode modulator according to the invention can thus cope with picture tubes (CRT) which require a very low amount of S-correction at a small scan width without the need for an additional capacitor (CS2) and a thyristor switching circuit (T) to activate the additional capacitor (CS2) to lower the amount of S-correction at the small scan width. The invention is particularly useful if a continuous zoom between a 16/9 and a 4/3 scan width on a display tube with a 16/9 aspect ratio has to be performed in a simple way.

    SCHALTUNGSANORDNUNG ZUM STEUERN DER SPEISESPANNUNG EINER BILDSIGNAL-ABLENKUNGSEINHEIT
    2.
    发明授权
    SCHALTUNGSANORDNUNG ZUM STEUERN DER SPEISESPANNUNG EINER BILDSIGNAL-ABLENKUNGSEINHEIT 有权
    电路,用于控制图像信号偏转装置的电源

    公开(公告)号:EP1230790B1

    公开(公告)日:2003-07-16

    申请号:EP00979558.4

    申请日:2000-11-14

    发明人: JESCHKE, Alfred

    IPC分类号: H04N3/27 H04N3/20

    CPC分类号: H04N3/20 H04N3/27

    摘要: The invention relates to a circuit arrangement for controlling the supply voltage (Ubvar) of a video signal deflection unit, especially a horizontal deflection unit (1) pertaining to a television apparatus or a monitor. The inventive arrangement comprises a control device (7) that receives a measured frequency signal (A) corresponding to the current frequency value of an input frequency (HSYNC) and a measured voltage signal (B) corresponding to the current voltage value of the supply voltage (Ubvar). The control device can adjust the operating frequency (D) of the video signal deflection unit (1) and the supply voltage (Ubvar) in an interdependent manner, according to said two measured signals (A, B) and in such a way that malfunctioning of the video signal deflection unit (1) is reliably prevented, whereby said operating frequency depends on the input frequency (HSYNC).

    Field synchronization system maintaining interlace integrity
    4.
    发明公开
    Field synchronization system maintaining interlace integrity 失效
    现场同步系统保持交错完整性

    公开(公告)号:EP1130909A3

    公开(公告)日:2001-10-24

    申请号:EP01111808.0

    申请日:1991-05-29

    IPC分类号: H04N5/44 H04N5/45

    摘要: First and second field type detectors for first and second video signals have outputs indicating whether the video signals have first or second field types. The first video signal is synchronized with the second video signal for a combined display by a synchronous field memory and an asynchronous multiple line memory. The field type of the second video signal is changed when necessary to match the field type of the first video signal to maintain interlace integrity in the combined display. A field type changing circuit, which controls the synchronizing, has a first mode of operation which delays writing a current field of the first field type by one horizontal line period, a second mode of operation which advances writing a current field of the second field type by one horizontal line period and a third mode of operation which maintains a current field type. A comparison of the field type of the second signal to the field type of the first signal results in an output signal indicating one of a plurality of comparison outcomes, wherein the first and second video signals have the same field type, wherein the first video signal has the first field type and the second video signal has the second field type and wherein the first video signal has the second field type and the second video signal ha the first field type. A plurality of selectable interlace correction signals are generated, each being appropriate for one of the plurality of comparison outcomes.

    摘要翻译: 用于第一和第二视频信号的第一和第二场型检测器具有指示视频信号是具有第一或第二场类型的输出。 第一视频信号与第二视频信号同步,以通过同步场存储器和异步多线存储器进行组合显示。 第二视频信号的场类型在必要时被改变以匹配第一视频信号的场类型以在组合显示中维持交织完整性。 控制同步的场类型改变电路具有第一操作模式和第二操作模式,第一操作模式延迟写入第一场类型的当前场一个水平行周期,第二操作模式推进写入第二场类型的当前场 通过一个水平线周期和维持当前场类型的第三操作模式。 第二信号的场类型与第一信号的场类型的比较导致指示多个比较结果中的一个的输出信号,其中第一和第二视频信号具有相同的场类型,其中第一视频信号 具有第一场类型并且第二视频信号具有第二场类型,并且其中第一视频信号具有第二场类型并且第二视频信号具有第一场类型。 产生多个可选择的交错校正信号,每个适合于多个比较结果中的一个。

    Display correction waveform generator for multiple scan frequencies
    5.
    发明公开
    Display correction waveform generator for multiple scan frequencies 审中-公开
    显示多个扫描频率的校正波形发生器

    公开(公告)号:EP1089557A3

    公开(公告)日:2001-07-04

    申请号:EP99125475.6

    申请日:1999-12-21

    IPC分类号: H04N3/26 H04N3/27 H04N3/233

    CPC分类号: H04N3/27 H04N3/2335 H04N3/26

    摘要: A method for generating display correction waveforms for a CRT display comprises the steps of selecting one of a plurality of trace portions for forming part of a correction waveform, the trace portions having different average values. Completing each of the correction waveform by combining each selected trace portion with a respective retrace portion such that all completed correction waveforms have a predetermined average value. The correction waveforms may have vertical and/or horizontal rates.

    摘要翻译: 一种用于产生CRT显示器的显示校正波形的方法包括以下步骤:选择用于形成校正波形的一部分的多个迹线部分中的一个,所述迹线部分具有不同的平均值。 通过将每个选择的迹线部分与相应的回扫部分组合来完成每个校正波形,使得所有完成的校正波形具有预定的平均值。 校正波形可以具有垂直和/或水平速率。

    Display frame rate adaptation
    7.
    发明公开
    Display frame rate adaptation 审中-公开
    Bildfrequenzanpassungfüreine Anzeige

    公开(公告)号:EP1073269A2

    公开(公告)日:2001-01-31

    申请号:EP00115835.1

    申请日:2000-07-24

    IPC分类号: H04N5/44

    摘要: An inventive method for adapting a display frame rate in a receiver to a picture frame rate of a received signal includes the steps of comparing a picture frame rate of a received signal with a display frame of a receiver, adjusting lines per field or lines per frame displayed in response to the comparing step, and generating a display frame rate control signal for the receiver in response to the adjusting step.

    摘要翻译: 将接收机中的显示帧速率适应于接收信号的图像帧速率的本发明的方法包括以下步骤:将接收信号的图像帧速率与接收机的显示帧进行比较,调整每帧的行或每帧的行数 响应于所述比较步骤显示,并响应于所述调整步骤产生所述接收机的显示帧速率控制信号。