Video synchronisation signal generation
    2.
    发明公开
    Video synchronisation signal generation 失效
    Videosynchronisierungssignalerzeugung。

    公开(公告)号:EP0463790A2

    公开(公告)日:1992-01-02

    申请号:EP91305534.9

    申请日:1991-06-19

    发明人: Herz, William S.

    IPC分类号: H04N5/06 H04N5/073

    CPC分类号: G09G5/12 H04N9/455

    摘要: A video synchronisation and frame pulse signal generator (10; 80; 90) generates a video synchronisation signal (36), such as a video black burst signal, and a video frame pulse signal (40) indicating the presence of a video signal frame. The generator (10; 80; 90) is self-contained and computer controllable and can be connected as a subsystem within an existing personal computer having an open architecture (e.g. as a plug-in interface board in a PC-AT (trade mark)). The video synchronisation signal (36) can be used as a master synchronisation signal source within a video signal processing system (e.g. an off-line video editing system). The video frame pulse signal (40) is synchronised to the video synchronisation signal (36) and can be selectively gated (22) under computer control to produce an interrupt signal useful as a stimulus for software interrupt routines of a computer within a video signal processing system. Computer controllable switches may be included for programmably selecting among additional video synchronisation and frame pulse signals (e.g. NTSC, PAL, SECAM or HDTV), which can be generated either internally or externally, the selected video synchronisation and frame pulse signals being used as the master synchronisation signal source and interrupt signal, respectively.

    摘要翻译: 视频同步和帧脉冲信号发生器(10; 80; 90)产生视频同步信号(36),诸如视频黑burst信号,以及指示视频信号帧的存在的视频帧脉冲信号(40)。 发电机(10; 80; 90)是独立的并且是计算机可控的,并且可以作为子系统连接在具有开放架构的现有个人计算机内(例如,作为PC-AT(商标)中的插件接口板) )。 视频同步信号(36)可以用作视频信号处理系统(例如离线视频编辑系统)内的主同步信号源。 视频帧脉冲信号(40)与视频同步信号(36)同步并且可以在计算机控制下选择性地选通(22),以产生一个中断信号,该中断信号可用作视频信号处理中计算机的软件中断程序的刺激 系统。 可以包括计算机可控开关,用于在可以在内部或外部生成的附加视频同步和帧脉冲信号(例如,NTSC,PAL,SECAM或HDTV)之间可编程选择所选择的视频同步和帧脉冲信号被用作主 同步信号源和中断信号。

    Digital chrominance signal processing circuit
    8.
    发明公开
    Digital chrominance signal processing circuit 失效
    Digitale Chrominanzsignalverarbeitungsschaltung。

    公开(公告)号:EP0198529A1

    公开(公告)日:1986-10-22

    申请号:EP86200458.7

    申请日:1986-03-20

    IPC分类号: H04N9/455 H04N9/64

    CPC分类号: H04N9/642 H04N9/455

    摘要: In a digital chrominance signal processing circuit for a chrominance signal which is sampled at a frequency equal to a number of times the chrominance subcarrier frequency, this frequency can be made variable, without switching to a different crystal frequency, by using a clock signal produced by a crystal oscillator (65) and a digital oscillator (71) which is controlled via a digital number (at 73) and whose quiescent frequency can be changed by changing a number to be applied to an input (95) of an adder circuit (85). Additionally, the adder circuit - (85) is supplied with a number representing a control signal (at 88) and applies via its output (83) the frequency-determining digital number to an input (73) of the digital oscillator (71).

    Procédé et circuit d'asservissement en fréquence et en phase d'un oscillateur local en télévision
    9.
    发明公开
    Procédé et circuit d'asservissement en fréquence et en phase d'un oscillateur local en télévision 失效
    方法和电路在电视本地振荡器的频率和Phasenverkopplung。

    公开(公告)号:EP0115234A1

    公开(公告)日:1984-08-08

    申请号:EP83402485.3

    申请日:1983-12-20

    申请人: THOMSON-CSF

    IPC分类号: H04N9/455 H03L7/10

    CPC分类号: H03L7/10 H04N9/455

    摘要: Ce circuit permet d'utiliser un oscillateur (1) sans préréglage pour réaliser un asservissement sur la sous-porteuse de chrominance d'un signal de télévision couleur. La sortie de l'oscillateur est comparée en phase dans un comparateur (7) à un signal de salve (6) sur lequel on veut effectuer l'asservissement. La sortie du comparateur (7) est envoyée par l'intermédiaire d'un amplificateur différentiel (9) à un circuit de commande à seuil (21) qui agit sur l'entrée de comptage (up) ou de décomptage (down) d'un compteur-décompteur (24) dont la sortie est transformée en signal analogique par un circuit (25) agissant sur l'entrée de commande (2) de l'oscillateur.

    Method and apparatus for measuring horizontal sync subcarrier phase
    10.
    发明公开
    Method and apparatus for measuring horizontal sync subcarrier phase 失效
    用于测量水平同步和子载波之间的相位关系的方法和装置。

    公开(公告)号:EP0090426A2

    公开(公告)日:1983-10-05

    申请号:EP83103188.5

    申请日:1983-03-30

    IPC分类号: H04N9/44

    CPC分类号: H04N9/455 H04N17/02

    摘要: The 50% point of the leading edge of sync is used to acquire the value of a color burst locked CW carrier, and a quadrature color burst locked CW carrier. The acquired value of each of the two carriers are split into two values representing the value on alternating horizontal lines. This requires the generation of a one-half horizontal rate signal (H/2) which can have an arbitrary phase relationship. The H/2 phase is associated with each of the four acquired CW carrier values and that information is used by a computing device. The H/2 signal is also used to gate a 30 Hz vertical frame pulse to generate a 15 HzV1 color frame pulse. The computing device receives the color frame pulse and records the time the pulse occurs. This information represents the minimum and sufficient set of data to obtain a complete measure of sync to subcarrier phase (SC/H) and color frame comparison. By multiplexing the acquisition electronics between two video sources, SC/H and color frame comparisons can be made by the computing device.