利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

584 条记录 (耗时 0.014 秒)

    MEDIA HARDWARE RESOURCE ALLOCATION
    2.
    发明授权
    MEDIA HARDWARE RESOURCE ALLOCATION 有权

    公开(公告)号：EP2909718B1

    公开(公告)日：2018-09-12

    申请号：EP13786790.9

    申请日：2013-10-18

    申请人： Advanced Micro Devices, Inc.

    发明人： SCHMIT, Michael L. ,  FARMER, Ashish

    IPC分类号： G06F9/50

    CPC分类号： G06F9/5044 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5027 ,  G06F9/505 ,  G06F9/5055 ,  Y02D10/22

    摘要： Apparatus, computer readable medium, and method of allocating media resources, the method including determining a media resources allocation table based on one or more media hardware resources and predetermined benchmarks of media hardware resources for performing media operations; in response to receiving a request for media resources from a first application, comparing the requested media resources with the media resources allocation table; and if the comparison indicates that the requested media resources are available, then allocating the requested media resources to the first application in the media resources allocation table, and sending a response to the request for media resources to the first application indicating the requested media resources are allocated to the application. If the comparison indicates that the requested media resources are not available, then sending indicating to the first application that the requested media resources are not allocated to the first application.

    POWER AWARE SCHEDULING AND POWER MANAGER
    6.
    发明公开
    POWER AWARE SCHEDULING AND POWER MANAGER 审中-公开
    POWER AWARE调度和电源管理器

    公开(公告)号：EP3278220A1

    公开(公告)日：2018-02-07

    申请号：EP16714717.2

    申请日：2016-03-28

    申请人： Microsoft Technology Licensing, LLC

    发明人： SHARDA, Vishal ,  WORTHINGTON, Bruce Lee

    IPC分类号： G06F9/48

    CPC分类号： G06F1/329 ,  G06F1/3203 ,  G06F9/4893 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

    摘要： A computing system having a plurality of processing units configured to perform work by having threads assigned to the processing units. A thread scheduler is coupled to the plurality of processors and configured to schedule threads to the processing units. A power manager is coupled to the thread scheduler and controls performance states or idle states of the processing units. The thread scheduler maintains information about current performance state or idle state per processing unit. The information includes a multi-level description of the processing units in the computing system. The multi-level description includes three or more different entry values of different levels for performance state or idle state for processing units. The power manager provides the multi-level description of the processing units to the thread scheduler, which is configured to schedule threads to the processing units based on the multi-level description.

    PROGRESS METERS IN PARALLEL COMPUTING
    7.
    发明公开
    PROGRESS METERS IN PARALLEL COMPUTING 审中-公开
    并行计算中的进度计

    公开(公告)号：EP3238059A1

    公开(公告)日：2017-11-01

    申请号：EP15874133.0

    申请日：2015-12-15

    申请人： Intel Corporation

    发明人： EASTEP, Jonathan M. ,  SHARAPOV, Ilya ,  VAN DER WIJNGAART, Rob F. ,  GRECO, Richard J. ,  SYLVESTER, Steve S. ,  LOMBARD, David N.

    IPC分类号： G06F9/50 ,  G06F9/48

    CPC分类号： G06F9/522 ,  G06F9/5083 ,  G06F9/5094 ,  G06F2209/508 ,  Y02D10/22

    摘要： Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.

    摘要翻译： 系统和方法可以提供一组能够并行执行线程的内核。 每个内核可以运行随进度计一起提供的代码，用于计算线程运行在各自内核上时剩余的工作量。 数据可以连续收集，并且可以用于改变内核以及内核组的频率，速度或其他操作特性。 进度表可以被注释到现有的代码中。

    Information processing apparatus, control method, and control program
    8.
    发明公开
    Information processing apparatus, control method, and control program 审中-公开
    信息处理设备，控制方法和控制程序

    公开(公告)号：EP2648069A3

    公开(公告)日：2017-09-06

    申请号：EP13161065.1

    申请日：2013-03-26

    申请人： FUJITSU LIMITED

    发明人： Yamana, Fumiaki ,  Kondou, Hiroshi ,  Gotsubo, Kenji

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3293 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/22

    摘要： An information processing apparatus includes a memory and a processor coupled to the memory. The processor is configured to: determine whether or not a difference between a total of power consumption values of physical or virtual computers and a preset upper-limit value satisfies a certain condition; select, in ascending order of priorities stored in a first storage and set based on details of processing executed by the computers, any of the computers as a target whose power consumption is to be reduced, when the difference satisfies the certain condition; and switch the computer selected to a state in which the power consumption is reduced.

    摘要翻译： 信息处理设备包括存储器和耦合到存储器的处理器。 处理器被配置为：确定物理或虚拟计算机的总功耗值与预设上限值之间的差值是否满足特定条件; 当所述差值满足所述特定条件时，按照存储在第一存储装置中的优先级从高到低的顺序选择并且基于所述计算机执行的处理的细节设置所述计算机中的任一个作为其功耗要降低的目标; 并将选择的计算机切换到功耗降低的状态。