Method of manufacturing lateral insulated-gate field-effect transistors
    5.
    发明公开
    Method of manufacturing lateral insulated-gate field-effect transistors 失效
    Verfahren zur Herstellung侧边的Feld-Effekt-Transistoren mit隔离门。

    公开(公告)号:EP0294885A2

    公开(公告)日:1988-12-14

    申请号:EP88201138.0

    申请日:1988-06-06

    摘要: A method of manufacturing a semiconductor device in which a lateral insulated gate field effect transistor (IGFET) (1) is provided by defining an insulated gate structure (12) on a given surface (3a) of a semiconductor body (3) by providing an insulating layer on the given surface (3a) having a relatively thin region on a first area of the given surface adjoining a relatively thick region (14a) on a second area (31b) of the given surface and providing a conductive layer (15,16) on the insulating layer to define an insulated gate over the first area of the given surface with the conductive layer extending up onto the relatively thick region of the insulating layer. A window (26) is opened in the conductive layer on the relatively thick region of the insulating layer and the insulating layer is then etched isotropically through the window in the conductive layer to form a window (25) in the relatively thick region of the insulating layer thereby leaving part (29) of the conductive layer overhanging the edge of the window in the insulating layer. The conductive layer is then selectively etched with at least the area of conductive layer spaced from the window masked so as to remove the part (29) overhanging the edge of the window (25) in the insulating layer. Impurities are then introduced using the insulated gate structure (12) as a mask to form a source region (9) aligned with the insulated gate and a drain region (10) aligned with the window in the conductive layer (15, 16).

    摘要翻译: 一种制造半导体器件的方法,其中通过在半导体本体(3)的给定表面(3a)上限定绝缘栅极结构(12)来提供横向绝缘栅场效应晶体管(IGFET)(1) 在给定表面上具有相对较薄区域的绝缘层,该给定表面在给定表面的第一区域上邻接给定表面的第二区域(31b)上的相对较厚的区域(14a),并提供导电层(15,16 ),以在给定表面的第一区域上限定绝缘栅极,导电层向上延伸到绝缘层的相对较厚的区域上。 在绝缘层的相对较厚的区域上的导电层中打开窗口(26),然后绝缘层通过导电层中的窗口各向同性地被蚀刻,以在绝缘层的相对较厚的区域中形成窗口(25) 从而使导电层的部分(29)悬垂在绝缘层中窗口的边缘上。 导电层然后被选择性地蚀刻至少与被掩蔽的窗口间隔开的导电层的区域,以便去除在绝缘层中悬垂在窗口(25)的边缘上的部分(29)。 然后使用绝缘栅极结构(12)作为掩模引入杂质以形成与绝缘栅极对准的源极区域(9)和与导电层(15,16)中的窗口对准的漏极区域(10)。

    Method of controlling gate oxide thickness in the fabrication of semiconductor devices
    6.
    发明公开
    Method of controlling gate oxide thickness in the fabrication of semiconductor devices 失效
    一种用于控制栅极氧化物的厚度为半导体器件的制造方法。

    公开(公告)号:EP0631308A3

    公开(公告)日:1996-06-12

    申请号:EP94108709.0

    申请日:1994-06-07

    IPC分类号: H01L21/82 H01L21/28

    摘要: A method of controlling gate oxide thickness in the fabrication of semiconductor devices wherein a sacrificial gate oxide layer is formed on a semiconductor substrate surface. Nitrogens ions are implanted into select locations of the substrate through the sacrificial gate oxide layer, and the substrate and the gate oxide layer are then thermally annealed. The sacrificial gate oxide layer is then removed and a gate oxide layer is then formed on the substrate layer wherein the portion of the gate oxide layer formed on the nitrogen ion implanted portion of the substrate is thinner than the portion of the gate oxide layer formed on the non-nitrogen ion implanted portion.

    摘要翻译: 控制栅氧化层厚度是半导体器件制造商包括在半导体衬底(10)的选定位置上形成牺牲栅极氧化物,注入N离子注入到选定位置穿过氧化,热退火,以帮助Ñ堆积在基板面, 和去除所述牺牲氧化物。 栅极氧化热生长在衬底上(26)和将大于其他地方(34)较薄在N个注入区(30)。 衬底为Si,氧化物层被形成和前牺牲层除去,N离子以10×13-10功率个电源17的离子厘米-2注入和退火是在800-1100℃温度为1-90 分钟。 栅极氧化物在800-1000℃温度下干燥O 2形成5-20分钟。

    METHOD FOR FORMING THIN TUNNELING WINDOWS IN EEPROMs.
    8.
    发明公开
    METHOD FOR FORMING THIN TUNNELING WINDOWS IN EEPROMs. 失效
    VERFAHREN ZUR AUSFORMUNGDÜNNERTUNNELFENSTER在EEPROM中。

    公开(公告)号:EP0664051A4

    公开(公告)日:1996-01-10

    申请号:EP94922441

    申请日:1994-06-17

    申请人: ATMEL CORP

    摘要: A method for making submicron dielectric windows (65) for electron tunneling between a floating gate (70) and substrate (15) in a semiconductor EEPROM device. A mask edge (35) overlying an oxide layer (25) on a substrate (15) is undercut a small distance (40), the area surrounding that small distance is built up with oxide (50), then a thin layer of oxide is formed in the undercut distance to serve as a tunneling window (65).

    摘要翻译: 一种用于在半导体EEPROM器件中制造浮栅和衬底之间的电子隧穿的亚微米电介质窗的方法。 覆盖衬底上的氧化物层的掩模边缘被切割小的距离,围绕该小距离的区域由氧化物构成,然后在底切距离处形成薄层的氧化物以用作隧道窗口。

    Method of manufacturing lateral insulated-gate field-effect transistors
    9.
    发明公开
    Method of manufacturing lateral insulated-gate field-effect transistors 失效
    制造侧向绝缘栅场效应晶体管的方法

    公开(公告)号:EP0294885A3

    公开(公告)日:1990-01-03

    申请号:EP88201138.0

    申请日:1988-06-06

    摘要: A method of manufacturing a semiconductor device in which a lateral insulated gate field effect transistor (IGFET) (1) is provided by defining an insulated gate structure (12) on a given surface (3a) of a semiconductor body (3) by providing an insulating layer on the given surface (3a) having a relatively thin region on a first area of the given surface adjoining a relatively thick region (14a) on a second area (31b) of the given surface and providing a conductive layer (15,16) on the insulating layer to define an insulated gate over the first area of the given surface with the conductive layer extending up onto the relatively thick region of the insulating layer. A window (26) is opened in the conductive layer on the relatively thick region of the insulating layer and the insulating layer is then etched isotropically through the window in the conductive layer to form a window (25) in the relatively thick region of the insulating layer thereby leaving part (29) of the conductive layer overhanging the edge of the window in the insulating layer. The conductive layer is then selectively etched with at least the area of conductive layer spaced from the window masked so as to remove the part (29) overhanging the edge of the window (25) in the insulating layer. Impurities are then introduced using the insulated gate structure (12) as a mask to form a source region (9) aligned with the insulated gate and a drain region (10) aligned with the window in the conductive layer (15, 16).