公开(公告)号：EP0057313A3

公开(公告)日：1982-08-25

申请号：EP81304888

申请日：1981-10-20

申请人： BURROUGHS CORPORATION (a Michigan corporation)

发明人： Dongsung, Robert Kim

IPC分类号： G06F09/42 ,  G06F09/46

CPC分类号： G06F9/4486

摘要： Multi-phase subroutine control apparatus for use in a data processing system which provides for the concurrent execution of a plurality of tasks in a multiprogramming and multiprocessing environment. Subroutine control operations are staged so as to share common hardware in a manner which in effect provides a plurality of phased concurrently operating subroutine control circuits wherein each circuit provides control for a different one of a plurality of concurrently executing tasks. The common subroutine hardware includes a multi-level stack for each task and a fast access return address register which permits a return address to be rapidly made available when required during execution of a task.

公开(公告)号：EP0057312A3

公开(公告)日：1982-08-18

申请号：EP81304886

申请日：1981-10-20

申请人： BURROUGHS CORPORATION (a Michigan corporation)

发明人： Dongsung, Robert Kim

IPC分类号： G06F09/42

CPC分类号： G06F9/4486

摘要： Subroutine control apparatus for providing shared subroutine control for a plurality of executing tasks. Multiple levels of subroutine entry are provided for each task by employing a plurality of selectably accessible stacks, one for each task, along with corresponding pointer registers. These provide storage for a plurality of return addresses as required for each task during task performance. In addition, an updatable significantly faster access register is provided for each task for storing its most recent return address so as to permit return addresses to be rapidly made available when an executing task reaches the end of a subroutine.

公开(公告)号：EP0150535A3

公开(公告)日：1985-08-21

申请号：EP84201883

申请日：1984-12-17

申请人： TELECOMMUNICATIONS RADIOELECTRIQUES ET TELEPHONIQUES T.R.T.

发明人： Mary, Luc ,  Barazesh, Bahman

IPC分类号： G06F09/40 ,  G06F09/42

CPC分类号： G06F9/325 ,  G06F9/4486

公开(公告)号：EP0100108A3

公开(公告)日：1986-08-27

申请号：EP83200430

申请日：1983-03-28

申请人： Rothstein, Robert

发明人： Rothstein, Robert

IPC分类号： G06F15/20 ,  G06F09/42

CPC分类号： G16H40/63 ,  G06F19/00 ,  G06F19/3418

摘要： @ A microprocessor-controlled interface for permitting any digital host computer to receive serial digital data from any instrument wherein (a) the time at which digital data from the instrument is to enter the host computer and (b) the logical structure of the digital data entering the host computer are controlled by instructions from the host computer to the microprocessor and wherein (a) physical formatting incompatibilities between the host computer and the instrument and (b) the communicating of prohibited characters from the instrument to the host computer and vice versa are avoided. The timing control and logical structure of the digital data are effected by directing data from the instrument into a scratchpad memory, which is divided into records pursuant to instructions from the host computer, the contents of the scratchpad memory being sent to the host computer upon a corresponding instruction therefrom. A terminal for communicating with the host computer and the instrument may be included. Physical formatting discrepancies are avoided by translating inputs to the interface into a common physical format and translating outputs from the interface into the physical format of the instrument, host computer, or terminal which is receiving such outputs. Because about 90% of all current digital devices are formatted in a manner translatable by a selected one of three translator elements, a small number of interfaces formatted for a specific host computer (and terminal) can be used with a vast number of different instruments by accounting only for the instrument physical format and associated prohibited characters. Instructions, selected from a set of distinct instructions, which are sent from the computer to the microprocessor determine (a) whether a terminal-host computer, instrument-host computer, or terminal-instrument communication channel is to be open, (b) whether all channels are to be closed, and (c) when other communication transfer operations are to be executed. Terminal-host computer communications can occur at least substantially simultaneously with the directing of digital data from the instrument to the scratchpad memory.

摘要翻译： 用于允许任何数字主机从任何仪器接收串行数字数据的微处理器控制接口，其中（a）来自仪器的数字数据进入主计算机的时间和（b）数字数据输入的逻辑结构 主计算机由从主计算机到微处理器的指令控制，并且其中（a）在主计算机和仪器之间的物理格式化不兼容性以及（b）禁止的字符从仪器到主计算机的通信以及反之亦然 。 数字数据的定时控制和逻辑结构通过将数据从仪器引导到暂存器存储器中来实现，该暂存器存储器根据来自主计算机的指令被分成记录，暂存器存储器的内容在一个 相应的指令。 可以包括用于与主机和仪器进行通信的终端。 通过将接口的输入转换为通用物理格式并将接口的输出转换为正在接收这种输出的仪器，主机或终端的物理格式来避免物理格式化差异。

公开(公告)号：EP0202848A3

公开(公告)日：1988-08-31

申请号：EP86303631

申请日：1986-05-13

申请人： FUJITSU LIMITED

发明人： Yamada, Kenji

IPC分类号： G06F09/46 ,  G06F09/42

CPC分类号： G06F9/462 ,  G06F9/4486

摘要： In a microcomputer a random access memory (12) and a central processor unit (11) are mounted on a single chip and are connected therebetween by a bus line (BUS). Bit lines (BL, BL) of the memory are extended to internal registers of the central processor unit, and a connecting portion (10) which can read and write is provided therebetween. When data bits from an internal register are saved, one word line of the memory is selected and all bits of the data are transferred simultaneously to a memory cell group connected to the word line.

公开(公告)号：EP0138352A3

公开(公告)日：1988-03-16

申请号：EP84305968

申请日：1984-08-31

申请人： UNISYS CORPORATION

发明人： Green, Howard Hunt ,  Tomlinson, Christopher Jerome

IPC分类号： G06F09/42 ,  G06F09/26

CPC分类号： G06F9/4486

摘要： © A method of operating a data processing system includes the steps of: executing one high level language software program until an instruction is encountered which calls and activity; sensing whether said encountered instruction is linked to the activity which it calls by a first type or a second type depictor; executing another high level language software program for performing the called activity if the sensing step detects the first type depictor; and activating a low level language microcode program or hardware logic circuit for performing the called activity if the sensing step detects the second type depictor.