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    APPARATUS AND METHOD FOR LOW LATENCY SWITCHING
    3.
    发明公开
    APPARATUS AND METHOD FOR LOW LATENCY SWITCHING 审中-实审

    公开(公告)号：EP4394614A2

    公开(公告)日：2024-07-03

    申请号：EP24175982.8

    申请日：2014-12-03

    申请人： Arista Networks, Inc.

    发明人： SNOWDON, David ,  THOMAS, Charles ,  McDAID, Scott ,  POWLES, Lindsay

    IPC分类号： G06F15/163

    CPC分类号： G06F13/00 ,  H04L12/413

    摘要： A method of data switching. Data is received at least one input port of a crosspoint switch. The crosspoint switch configurably casts the data to at least one output port of the crosspoint switch. The or each output port of the crosspoint switch is connected to a respective input of a logic function device such as a FPGA. The logic function device applies a logic function to data received from the or each output port of the crosspoint switch, such as address filtering or multiplexing, and outputs processed data to one or more respective logic function device output interfaces. Also, a method of switching involving circuit switching received data to an output while also copying the data to a higher layer function.

    NETWORK-ON-CHIP DATA PROCESSING METHOD AND DEVICE
    8.
    发明公开
    NETWORK-ON-CHIP DATA PROCESSING METHOD AND DEVICE 审中-公开

    公开(公告)号：EP4009186A1

    公开(公告)日：2022-06-08

    申请号：EP21217804.0

    申请日：2019-10-18

    申请人： Shanghai Cambricon Information Technology Co., Ltd

    发明人： ZHANG, Yao ,  LIU, Shaoli ,  LIANG, Jun ,  CHEN, Yu ,  LI, Zhen

    IPC分类号： G06F15/78 ,  G06F15/163 ,  G06N3/063 ,  G06N3/08 ,  G06F15/173

    摘要： The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system, and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

    INTER-CORE DATA PROCESSING METHOD AND SYSTEM, SYSTEM ON CHIP AND ELECTRONIC DEVICE
    9.
    发明公开
    INTER-CORE DATA PROCESSING METHOD AND SYSTEM, SYSTEM ON CHIP AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：EP3979088A1

    公开(公告)日：2022-04-06

    申请号：EP20883486.1

    申请日：2020-10-19

    申请人： GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.

    发明人： ZHOU, Feng ,  FANG, Pan ,  CHEN, Yan

    IPC分类号： G06F15/163 ,  G06F15/167

    摘要： Disclosed are an inter-core data processing method and system, a system on chip, and an electronic device. The method comprises: a first core sends, by means of a command transmission module, to a second core a first command indicating that the first core is ready to perform a data processing operation corresponding to a target address; the second core acquires a mutex corresponding to the target address in response to the first command and returns a second command to the first core by means of the command transmission module; and the first core performs the data processing operation corresponding to the target address by means of a bus module in response to the second command. In this way, the first core and the second core can first complete the command interaction by means of the command transmission module, and then perform data operation interaction by means of the bus module after the second core acquires the mutex lock, so that the first core and the second core would not operate on the same address, thereby preventing data errors and improving the stability of data operations even in the case of low-power bus communication between the first core and the second core.