METHOD AND SYSTEM FOR PROCESSING AN ANALOG SIGNAL

    公开(公告)号:EP4383563A1

    公开(公告)日:2024-06-12

    申请号:EP22212155.0

    申请日:2022-12-08

    IPC分类号: H03F1/26 H03F3/181 H03F3/38

    CPC分类号: H03F3/38 H03F3/181 H03F1/26

    摘要: A method (100) for processing an analog signal is provided. The method comprises the steps of modulating (101) the analog signal using a chopping signal with a chopping frequency fchop to generate a modulated signal, amplifying (102) the modulated signal to generate an amplified signal, low-pass filtering (103) the amplified signal to generate a filtered signal comprising at least one harmonic of the modulated signal, and sub-sampling (104) the filtered signal and performing correlated double sampling operation by subtracting the samples at the chopping frequency.

    CHOPPER AMPLIFIERS WITH TRACKING OF MULTIPLE INPUT OFFSETS

    公开(公告)号:EP3920414A1

    公开(公告)日:2021-12-08

    申请号:EP21177476.5

    申请日:2021-06-02

    发明人: KUSUDA, Yoshinori

    摘要: Chopper amplifiers with tracking of multiple input offsets are disclosed herein. In certain embodiments, a chopper amplifier includes chopper amplifier circuitry including an input chopping circuit, an amplification circuit, and an output chopping circuit electrically connected along a signal path. The amplification circuit includes two or more pairs of input transistors, from which a control circuit chooses a selected pair of input transistors to amplify an input signal. The chopper amplifier further incudes an offset correction circuit that senses the signal path to generate an input offset compensation signal for the amplification circuit. Furthermore, the offset correction circuit separately tracks an input offset of each of the two or more pairs of input transistors.

    HIGH-LINEARITY DIFFERENTIAL TO SINGLE ENDED BUFFER AMPLIFIER

    公开(公告)号:EP3896849A1

    公开(公告)日:2021-10-20

    申请号:EP21165919.8

    申请日:2021-03-30

    申请人: MediaTek Inc.

    IPC分类号: H03F3/45 H03F1/32 H03F1/26

    摘要: A differential to single-ended buffer amplifier (300) with a swing suppression resistor (Rss) in the differential amplification architecture is shown. The differential to single-ended buffer amplifier (300) has a positive input terminal, a negative input terminal, a differential to single-ended operational amplifier (DISO op amp), and a swing suppression resistor (Rss). The DISO op amp has a non-inverting input terminal and an inverting input terminal respectively coupled to the positive input terminal and the negative input terminal, and it has a single-ended output terminal that outputs the output signal (Vout) of the differential to single-ended buffer amplifier (300). The swing suppression resistor (Rss) is connected between the negative input terminal of the differential to single-ended buffer amplifier and the non-inverting input terminal of the DISO op amp.