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    Dual port voltage controlled emitter coupled multivibrator
    2.
    发明公开
    Dual port voltage controlled emitter coupled multivibrator 失效
    Spannungskontrollierter emittergekoppelter Multivibrator mit zweiEingängen。

    公开(公告)号：EP0383194A1

    公开(公告)日：1990-08-22

    申请号：EP90102468.7

    申请日：1990-02-08

    申请人： NATIONAL SEMICONDUCTOR CORPORATION

    发明人： Menon, Suresh ,  Murthi, Enjeti

    IPC分类号： H03K3/281 ,  H03K3/297

    CPC分类号： H03K3/011 ,  H03K3/2821

    摘要： A voltage controlled oscillator includes an emitter coupled multivibrator in which a capacitor determines the frequency of oscillation along with a pair of load resistors (14, 15) and a pair of current sources (16, 17). A differential amplifier (20, 21) is coupled to operate in parallel with the multivibrator and its tail current is oper­ated differentially, with respect to the currents in the pair of sources (16, 17), in response to the input voltage at a first modulation input port. Thus, a constant current flows in the multivibrator loads even when the frequency is modulated. A second input port is coupled to vary the tail current in the differential amplifier to comprise a dual port control of the voltage controlled oscil­lator. The circuit can be operated at a relatively low supply voltage and can be temperature compensated. Furthermore, the input ports can include circuitry having a logarithimic response for digital signaling processing.

    摘要翻译： 压控振荡器包括发射极耦合多谐振荡器，其中电容器与一对负载电阻器（14,15）和一对电流源（16,17）一起确定振荡频率。 差分放大器（20,21）被耦合以与多谐振荡器并联操作，并且其尾电流相对于一对源（16,17）中的电流被差分地操作，响应于第一 调制输入端口。 因此，即使在频率被调制时，恒定电流也流入多谐振荡器负载。 耦合第二输入端口以改变差分放大器中的尾部电流，以包括压控振荡器的双端口控制。 该电路可以在相对较低的电源电压下工作，并可进行温度补偿。 此外，输入端口可以包括具有用于数字信号处理的对数响应的电路。

    Flip-flop having improved synchronous reset
    3.
    发明公开
    Flip-flop having improved synchronous reset 失效
    与同步复位失败。

    公开(公告)号：EP0127858A1

    公开(公告)日：1984-12-12

    申请号：EP84105995.9

    申请日：1984-05-25

    申请人： MOTOROLA, INC.

    发明人： Birch, William A. ,  Woodard, Lillie M.

    IPC分类号： H03K3/037 ,  H03K3/281

    CPC分类号： H03K3/289 ,  H03K3/0372

    摘要： A flip-flop is provided having a data gate circuit means (1) for receiving input data and generating therefrom first and second complementary internal data signals representative of the input data. A master circuit means (2) is coupled to the data gate circuit means for receiving a clock pulse and for latching the internal data signals during a predetermined portion of the clock pulse. A slave circuit means (3) is coupled to the master circuit means for storing the internal data signals. A reset means (23) supplies a synchronous reset signal to the master circuit means for resetting the first and second complementary internal data signals on the occurrence of the next clock pulse.