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公开(公告)号：EP1643772A3
公开(公告)日：2011-01-19
申请号：EP05017396.2
申请日：2005-08-10
申请人： Broadcom Corporation
CPC分类号： H04N7/50 , H04N5/505 , H04N7/56 , H04N19/61 , H04N21/23406 , H04N21/23424 , H04N21/4305 , H04N21/4384 , H04N21/44004 , H04N21/44016
摘要： Presented herein are system(s) and method(s) for clean channel changes. In one embodiment, there is presented a method for changing a channel. The method comprises receiving a portion of a first video bitstream associated with a first channel; receiving a command to switch display from the first channel to a second channel after receiving the portion of the first video; and displaying the portion of the first video bitstream associated with the first channel after receiving the command.
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3.发明公开Image processing apparatus and method using padding data 审中-公开Bildverarbeitungsvorrichtung und -verfahren mit Verwendung vonFülldaten
公开(公告)号：EP1988713A1
公开(公告)日：2008-11-05
申请号：EP07107210.2
申请日：2007-04-30
发明人： McNaughton, Craig
CPC分类号： H04N21/4344 , H04N7/56 , H04N19/00 , H04N21/2343 , H04N21/2353 , H04N21/236 , H04N21/23608 , H04N21/23611 , H04N21/4348
摘要： An image processing apparatus (100) comprises an encoder processor (102) and a decoder circuit (104). The encoder processor (102) receives image data from a sensor (106) and encodes the data with padding data if should a series of bytes indicative of command sequence occur within the image data. The decoder circuit (104) receives the image data and the padding data, and removes the padding data from within the image data.
摘要翻译： 图像处理装置（100）包括编码器处理器（102）和解码器电路（104）。 编码器处理器（102）从传感器（106）接收图像数据，并且如果应当在图像数据内发生表示命令序列的一系列字节，则用填充数据对数据进行编码。 解码器电路（104）接收图像数据和填充数据，并从图像数据内移除填补数据。
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公开(公告)号：EP1755263A3
公开(公告)日：2008-04-02
申请号：EP06023631.2
申请日：1997-03-18
发明人： Kikuchi, Yoshihiro c/o Toshiba Corp.;Int.Prop.Div. , Watanabe, Toshiaki c/o Toshiba Corporation , Dachiku, Kenshi c/o Toshiba Corp., Int.Prop.Div. , Chujoh, Takeshi , Nagai, Takeshi
CPC分类号： H04N7/56 , G11B27/3027 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0045 , H04L1/0075 , H04L1/0083 , H04N19/61 , H04N19/68 , H04N19/89 , H04N21/234318 , H04N21/235 , H04N21/2383 , H04N21/2404 , H04N21/242 , H04N21/4307 , H04N21/435
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
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公开(公告)号：EP1755264A2
公开(公告)日：2007-02-21
申请号：EP06023632.0
申请日：1997-03-18
CPC分类号： H04N7/56 , G11B27/3027 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0045 , H04L1/0075 , H04L1/0083 , H04N19/61 , H04N19/68 , H04N19/89 , H04N21/234318 , H04N21/235 , H04N21/2383 , H04N21/2404 , H04N21/242 , H04N21/4307 , H04N21/435
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
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公开(公告)号：EP1755261A2
公开(公告)日：2007-02-21
申请号：EP06023629.6
申请日：1997-03-18
CPC分类号： H04N7/56 , G11B27/3027 , H04J3/0602 , H04J3/0605 , H04J3/07 , H04L1/004 , H04L1/0041 , H04L1/0045 , H04L1/0075 , H04L1/0083 , H04N19/61 , H04N19/68 , H04N19/89 , H04N21/234318 , H04N21/235 , H04N21/2383 , H04N21/2404 , H04N21/242 , H04N21/4307 , H04N21/435
摘要： In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detection are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting-/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.
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公开(公告)号：EP0760562B1
公开(公告)日：2004-10-27
申请号：EP96306320.1
申请日：1996-08-30
发明人： Shioi, Masahiro , Hibi, Keiichi , Nakabayashi, Jiro , Iwano, Tsuneaki , Nakamura, Osamu , Kanada, Youji , Kura, Tsuneko , Oshima, Takashi
CPC分类号： H04J3/0605 , H04N7/56
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公开(公告)号：EP0708567A3
公开(公告)日：2000-10-25
申请号：EP95307182.6
申请日：1995-10-11
申请人： AT&T Corp.
IPC分类号： H04N7/56
CPC分类号： H04N21/4302 , H04N7/56 , H04N21/23614 , H04N21/4348 , H04N21/44004 , H04N21/6336
摘要： A method is provided for synchronizing video data buffers (14,18) in a system containing a variable rate transmission channel (16), including: an encoder (12) for encoding input data into a compressed data bitstream, an encoder buffer (14) for storing the compressed data bitstream. a decoder buffer (18) for receiving the compressed data bitstream, the sum of the encoder buffer delay and the decoder buffer delay being constant, and a decoder (20) for receiving and decoding the compressed data bitstream. The instantaneous encoder buffer delay is used to generate a control signal which is inserted into the compressed data bitstream following the encoder buffer. In an exemplary embodiment, each of the encoder and decoder performs encoding and decoding operations, respectively, in the Motion Picture Experts Group (MPEG) standard, using the VBV_DLY parameter of the MPEG standard as the control signal.
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9.发明授权
公开(公告)号：EP0634870B1
公开(公告)日：1999-04-28
申请号：EP94303735.8
申请日：1994-05-25
发明人： Moriyama, Yoshiaki, c/o Corporate Research and , Ono, Kouichi, c/o Corporate Research and , Hosaka, Sumio, c/o Pioneer Tokorozawa Plant , Yamada, Takao, c/o Pioneer Tokorozawa Plant
CPC分类号： H04N21/4341 , H04N21/4307
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公开(公告)号：EP0683604A3
公开(公告)日：1998-10-28
申请号：EP95107007
申请日：1995-05-09
IPC分类号： H04N5/04 , H04N5/44 , H04N5/60 , H04N5/92 , H04N5/93 , H04N7/04 , H04N7/045 , H04N7/08 , H04N7/081 , H04N7/12 , H04N7/26 , H04N7/52 , H04N7/56
CPC分类号： H04N21/4305 , H04N5/04 , H04N5/4401 , H04N5/602 , H04N7/56 , H04N21/4307 , H04N21/4396
摘要： A compressed audio/video, A/V, receiver provides A/V component timing reference signals (208,212,214,220,222) (PTS's) coincident with reproduction of associated decompressed component signals. Synchronization apparatus generates a function of the difference (217-219) of occurring component audio and video PTS's. This function, which is indicative of relative audio and video synchronization, is compared with a predetermined threshold value (225), and a mute control signal is generated when the threshold is exceeded. Muting circuitry (229), responsive to the control signal disables audio reproduction when the reproduced audio and video component signal timing deviate from mutual synchronization.
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