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    RFID PART AUTHENTICATION AND TRACKING OF PROCESSING COMPONENTS
    1.
    发明公开
    RFID PART AUTHENTICATION AND TRACKING OF PROCESSING COMPONENTS 审中-公开

    公开(公告)号：EP3982395A1

    公开(公告)日：2022-04-13

    申请号：EP21212586.8

    申请日：2017-11-15

    申请人： Applied Materials, Inc.

    发明人： HUNTER, Earl ,  DUKE, Russel ,  PURI, Amitabh ,  REEDY, Steven M.

    IPC分类号： H01L21/304 ,  H01L21/67 ,  B24B1/00 ,  B24B37/20 ,  B24B37/30 ,  B24B37/005 ,  G05B19/042

    摘要： Embodiments provided herein provide for methods and apparatus for detecting, authenticating, and tracking processing components including consumable components or non-consumable components used on substrate processing systems for electronic device manufacturing, such as semiconductor chip manufacturing. The semiconductor processing systems and/or its processing components herein include a remote communication device, such as a wireless communication apparatus, for example radio frequency identification (RFID) devices or other devices embedded in, disposed in, disposed on, located on, or otherwise coupled to one or more processing components or processing component assemblies and/or integrated within the semiconductor processing system itself. The processing component may include a single component (part) or an assembly of components (parts) that are used within the semiconductor processing tool.

    POLISHING PAD AND METHOD FOR PRODUCING SAME
    5.
    发明公开
    POLISHING PAD AND METHOD FOR PRODUCING SAME 有权
    抛光垫上，及其制造方法

    公开(公告)号：EP2806453A4

    公开(公告)日：2015-07-22

    申请号：EP12841356

    申请日：2012-10-12

    申请人： FUJIBO HOLDINGS INC

    发明人： ITOYAMA KOUKI ,  MIYAZAWA FUMIO

    IPC分类号： H01L21/304 ,  B24B37/20 ,  B24B37/24 ,  C08G18/32

    CPC分类号： B24B37/24 ,  C08G18/3814 ,  C08G18/4854 ,  C08G18/7621 ,  C08G2101/00 ,  C08G2101/0066 ,  C08K2201/005 ,  H01L21/31053 ,  C08G18/10 ,  C08G18/6685 ,  C08G18/3206

    摘要： Provided are: a polishing pad which is capable of alleviating a scratch problem that occurs when a conventional hard (dry) polishing pad is used, and which is excellent in polishing rate and polishing uniformity and is usable not only for primary polishing but also for finish polishing; and a method for producing the polishing pad. The polishing pad is for polishing a semiconductor device and includes a polishing layer having a polyurethane-polyurea resin molded body containing cells of a substantially spherical shape. The polyurethane-polyurea resin molded body has a ratio of closed cells of 60 to 98%. The polyurethane-polyurea resin molded body has a ratio tan´ of a loss modulus E" to a storage modulus E' (loss modulus/storage modulus) of 0.15 to 0.30. The storage modulus E' is 1 to 100 MPa. The polyurethane-polyurea resin molded body has a density D of 0.4 to 0.8 g/cm 3 .

    POLISHING PAD AND METHOD FOR PRODUCING SAME
    6.
    发明公开
    POLISHING PAD AND METHOD FOR PRODUCING SAME 有权
    VERFAHREN ZU SEINER HERSTELLUNG的POLIERKISSEN

    公开(公告)号：EP2806453A1

    公开(公告)日：2014-11-26

    申请号：EP12841356.4

    申请日：2012-10-12

    申请人： Fujibo Holdings, Inc.

    发明人： ITOYAMA Kouki ,  MIYAZAWA Fumio

    IPC分类号： H01L21/304 ,  B24B37/20 ,  B24B37/24 ,  C08G18/32

    CPC分类号： B24B37/24 ,  C08G18/3814 ,  C08G18/4854 ,  C08G18/7621 ,  C08G2101/00 ,  C08G2101/0066 ,  C08K2201/005 ,  H01L21/31053 ,  C08G18/10 ,  C08G18/6685 ,  C08G18/3206

    摘要： Provided are: a polishing pad which is capable of alleviating a scratch problem that occurs when a conventional hard (dry) polishing pad is used, and which is excellent in polishing rate and polishing uniformity and is usable not only for primary polishing but also for finish polishing; and a method for producing the polishing pad. The polishing pad is for polishing a semiconductor device and includes a polishing layer having a polyurethane-polyurea resin molded body containing cells of a substantially spherical shape. The polyurethane-polyurea resin molded body has a ratio of closed cells of 60 to 98%. The polyurethane-polyurea resin molded body has a ratio tanδ of a loss modulus E" to a storage modulus E' (loss modulus/storage modulus) of 0.15 to 0.30. The storage modulus E' is 1 to 100 MPa. The polyurethane-polyurea resin molded body has a density D of 0.4 to 0.8 g/cm 3 .

    摘要翻译： 本发明提供一种抛光垫，其能够减轻使用传统的硬（干）抛光垫时发生的划痕问题，抛光速度和抛光均匀性优异，不仅可用于一次抛光，而且可用于光洁度 抛光; 以及抛光垫的制造方法。 抛光垫用于抛光半导体器件，并且包括具有聚氨酯 - 聚脲树脂成型体的抛光层，所述聚氨酯 - 聚脲树脂成型体包含大致球形的电池。 聚氨酯 - 聚脲树脂成型体的闭孔率为60〜98％。 聚氨酯 - 聚脲树脂成型体的损耗模量E“与储能模量E'（损耗模量/储能模量）之比tan'为0.15〜0.30，储能模量E'为1〜100MPa， 聚脲树脂成型体的密度D为0.4〜0.8g / cm 3。

    Interconnected-multi-element-lattice polishing pad
    8.
    发明公开
    Interconnected-multi-element-lattice polishing pad 审中-公开
    。。。。。。。。。。。。。

    公开(公告)号：EP2025457A3

    公开(公告)日：2014-08-20

    申请号：EP08162350.6

    申请日：2008-08-14

    申请人： Rohm and Haas Electronic Materials CMP Holdings, Inc.

    发明人： Jiang, Bo ,  Muldowney, Gregory P.

    IPC分类号： B24B37/20

    CPC分类号： B01L3/502707 ,  B01L2200/0689 ,  B01L2300/0636 ,  B01L2300/0645 ,  B01L2300/0861 ,  B01L2300/0877 ,  B01L2300/123 ,  B24B37/24 ,  B24B37/26 ,  B33Y80/00

    摘要： The polishing pad (104) is useful for polishing at least one of magnetic, optical and semiconductor substrates (112) in the presence of a polishing medium (120). The polishing pad (104) includes a plurality of polishing elements (402, 502, 602, 702). The polishing elements (402, 502, 602, 702) are aligned in a vertical direction and having a first and a second end. A plurality of junctions (404, 510, 610, 710) connects the first and second ends of the polishing elements (402, 502, 602, 702) with at least three polishing elements at each of the plurality of junctions (404, 510, 610, 710) for forming a tier. Each tier representing a thickness in the vertical direction between the first and second ends of the polishing elements (402, 502, 602, 702). And an interconnected lattice structure (400, 600) forms from connecting sequential tiers of the plurality of junctions (404, 504) that connect the polishing elements (402, 502, 602, 702).

    摘要翻译： 抛光垫（104）可用于在抛光介质（120）的存在下抛光磁性，光学和半导体衬底（112）中的至少一种。 抛光垫（104）包括多个抛光元件（402,502,602,702）。 抛光元件（402,502,602,702）在垂直方向上对准并且具有第一端和第二端。 多个接头（404,510,610,710）将抛光元件（402,502,602,702）的第一和第二端与至少三个抛光元件连接在多个接合部（404,510,620,702） 610,610），用于形成层。 每个层代表在抛光元件（402,502,602,702）的第一和第二端之间的垂直方向上的厚度。 并且从连接抛光元件（402,502,602,702）的多个连接点（404,504）的顺序层连接形成互连的格子结构（400,600）。

    POLISHING PAD
    9.
    发明公开
    POLISHING PAD 审中-公开
    抛光垫

    公开(公告)号：EP2757577A1

    公开(公告)日：2014-07-23

    申请号：EP12831282.4

    申请日：2012-09-14

    申请人： Toray Industries, Inc.

    发明人： HONDA, Tomoyuki ,  FUKUDA, Seiji ,  OKUDA, Ryoji

    IPC分类号： H01L21/304 ,  B24B37/20 ,  B24B37/26

    CPC分类号： B24B37/26 ,  B24B37/20 ,  B24B37/22 ,  H01L21/304

    摘要： To suppress an increase in a polishing rate and deterioration of uniformity within a plane in a wafer due to shortage of the polishing rate in a central part of the wafer, a polishing pad at least includes a polishing layer, and a cushion layer, in which a plurality of holes is provided in the polishing layer, the holes passing through the polishing layer in a thickness direction, and a plurality of grooves is provided in a polishing surface of the polishing layer, a through hole ratio is from 0.13% or more to 2.1% or less, and angles made by the polishing surface and side surfaces of the groove, which continue to the polishing surface, is from 105 degrees or more to 150 degrees or less.

    摘要翻译： 为了抑制由于晶片中央部的研磨速度不足而引起的晶片内的研磨速度的上升和均匀性的降低，研磨垫至少具有研磨层和缓冲层，其中， 在研磨层中设置有多个孔，该多个孔在厚度方向上贯通研磨层，在研磨层的研磨面上设置有多个槽，通孔率为0.13％以上 2.1％或更少，并且与研磨表面连续的研磨表面和槽的侧表面形成的角度为105度以上至150度以下。