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103 条记录 (耗时 0.013 秒)

    UNIVERSAL-VOLTAGE DISCRETE INPUT CIRCUIT
    2.
    发明公开
    UNIVERSAL-VOLTAGE DISCRETE INPUT CIRCUIT 审中-公开

    公开(公告)号：EP2622725A4

    公开(公告)日：2018-02-14

    申请号：EP11831119

    申请日：2011-08-23

    申请人： COOPER TECHNOLOGIES CO

    发明人： KLETTI DANIEL RIAN ,  KROMREY TIMOTHY MARK

    IPC分类号： G05F3/16 ,  G05F3/18

    CPC分类号： G05F3/18

    摘要： A universal-voltage discrete input circuit uses a high voltage depletion-mode field effect transistor in combination with a low-voltage, adjustable precision shunt regulator and an isolation circuit for interfacing a low voltage digital logic circuit to a switched external voltage ranging from about 7 volts to about 1000 volts AC or +/− DC, at a low fixed current. In addition to the wide input voltage range accepted at a uniform low current value, very high voltage isolation is provided between the external voltage and the low voltage digital logic circuit, and elimination of ground loops and common mode noise.

    METHOD AND APPARATUS FOR CONTROLLING AN IGBT DEVICE
    3.
    发明公开
    METHOD AND APPARATUS FOR CONTROLLING AN IGBT DEVICE 有权
    VERFAHREN UND VORRICHTUNG ZUR STEUERUNG EINER IGBT-VORRICHTUNG

    公开(公告)号：EP3072026A4

    公开(公告)日：2017-07-19

    申请号：EP13897831

    申请日：2013-11-22

    申请人： NXP USA INC

    发明人： SICARD THIERRY ,  PERRUCHOUD PHILIPPE

    IPC分类号： G05F3/16 ,  H03K17/605

    CPC分类号： H03K17/567 ,  H03K17/163 ,  H03K17/168 ,  H03K17/605 ,  H03K17/689

    摘要： The present invention comprises a method and apparatus for controlling an IGBT device. The method comprises, upon receipt of a first and at least one further IGBT control signals, the first IGBT control signal indicating a required change in operating state of the IGBT device, controlling an IGBT driver module for the IGBT device to change an operating state of the IGBT device by applying a first logical state modulation at an input of an IGBT coupling channel, and applying at least one further modulation to the logical state at the input of the IGBT coupling channel in accordance with the at least one further IGBT control signal within a time period from the first logical state modulation, the time period being less than a state change reaction period Δt for the at least one IGBT device.

    摘要翻译： 本发明包括用于控制IGBT器件的方法和设备。 该方法包括：在接收到第一和至少一个另外的IGBT控制信号时，第一IGBT控制信号指示IGBT器件的操作状态中的所需变化;控制用于IGBT器件的IGBT驱动器模块，以改变IGBT器件的操作状态 所述IGBT器件通过在IGBT耦合沟道的输入处应用第一逻辑状态调制，并且根据所述IGBT耦合沟道的输入端处的所述至少一个另外的IGBT控制信号对所述逻辑状态施加至少一个另外的调制 从所述第一逻辑状态调制开始的时间段，所述时间段小于所述至少一个IGBT器件的状态改变反应时间段Δt。

    TEMPERATURE-COMPENSATED CURRENT REFERENCE CIRCUIT
    4.
    发明公开
    TEMPERATURE-COMPENSATED CURRENT REFERENCE CIRCUIT 审中-公开
    温度补偿参考电流电路

    公开(公告)号：EP1561153A4

    公开(公告)日：2007-08-01

    申请号：EP03749655

    申请日：2003-09-12

    申请人： ATMEL CORP

    发明人： ODDONE GIORGIO ,  BEDARIDA LORENZO ,  CHINOSI MAURO

    IPC分类号： G05F1/10 ,  G05F3/26 ,  G05F3/02 ,  G05F3/16 ,  G05F3/24

    CPC分类号： G05F3/245

    摘要： A current-reference circuit comprises a CMOS differential amplifier having first output node comprising a drain of a first n-channel MOS transistor and a second output node comprising a drain of a second n-channel MOS transistor. A first p-channel MOS transistor has a source coupled to a supply potential, a gate coupled to the second output node, and a drain. A first PNP bipolar transistor has an emitter coupled to the drain of the first p-channel MOS transistor through a first resistor and to a gate of the second n-channel MOS transistor, and a collector and a base both coupled to ground. A second PNP bipolar transistor has an emitter coupled to the drain of the first p-channel MOS transistor through a second resistor in series with a third resistor, and a collector and a base both coupled to ground. The gate of the first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor has a drain coupled to the drain of the first p-channel MOS transistor, a source coupled to ground through a fourth resistor, and a gate coupled to either a reference potential or to the common node between the second and third resistors.

    SYSTEM FOR CONTROLLING MODE CHANGES IN A VOLTAGE DOWN-CONVERTER
    5.
    发明公开
    SYSTEM FOR CONTROLLING MODE CHANGES IN A VOLTAGE DOWN-CONVERTER 审中-公开
    系统，以控制模式改变处于断电转换器

    公开(公告)号：EP1547088A4

    公开(公告)日：2007-05-02

    申请号：EP03754491

    申请日：2003-09-10

    申请人： ATMEL CORP

    发明人： SIVERO STEFANO ,  RIVA REGGIORI RICCARDO ,  TASSAN CASER FABIO

    IPC分类号： G11C11/413 ,  G05F1/56 ,  G11C5/14 ,  G11C7/00 ,  G05F1/10 ,  G05F3/02 ,  G05F3/16 ,  G05F3/20

    CPC分类号： G11C5/147

    摘要： A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node (68) is configured to receive a charge. A first transistor (54) has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch (58) is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor (66) is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch (64) is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.

    SYSTEM FOR CONTROLLING MODE CHANGES IN A VOLTAGE DOWN-CONVERTER
    6.
    发明公开
    SYSTEM FOR CONTROLLING MODE CHANGES IN A VOLTAGE DOWN-CONVERTER 审中-公开
    系统，以控制模式改变处于断电转换器

    公开(公告)号：EP1547088A1

    公开(公告)日：2005-06-29

    申请号：EP03754491.3

    申请日：2003-09-10

    申请人： ATMEL CORPORATION

    发明人： SIVERO, Stefano ,  RIVA REGGIORI, Riccardo ,  TASSAN CASER, Fabio

    IPC分类号： G11C7/00 ,  G05F1/10 ,  G05F3/02 ,  G05F3/16 ,  G05F3/20

    CPC分类号： G11C5/147

    摘要： A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node (68) is configured to receive a charge. A first transistor (54) has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch (58) is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor (66) is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch (64) is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.

    Power controller and power controlling method
    7.
    发明公开
    Power controller and power controlling method 审中-公开
    功率控制和功率控制方法

    公开(公告)号：EP1187294A3

    公开(公告)日：2004-07-28

    申请号：EP01120592.9

    申请日：2001-08-29

    申请人： NEC Electronics Corporation

    发明人： Nishiyama, Yoshikazu

    IPC分类号： G05F3/16

    CPC分类号： H02M3/155 ,  G05F3/30 ,  H02M2003/1555 ,  H03K17/063 ,  H03K17/0822 ,  H03K17/102

    摘要： A power controller comprises : a first control signal generator operable with a second power voltage for generating a first control signal ; a first reference voltage generator operable with a first power voltage for generating a first reference voltage corresponding to a difference between the first and second power voltages ; a first level converter coupled with the first control signal generator for receiving the first control signal, the first level converter coupled with the first reference voltage generator for converting the first control signal into a first level-converted control signal with a voltage level range between the first power voltage and the difference between the first and second power voltages ; and a first driver coupled with thc first level converter for receiving the first level-converted control signal, and the first driver driving an external load with the first level-converted control signal.

    TEMPERATURE INDEPENDENT CURRENT REFERENCE
    8.
    发明公开
    TEMPERATURE INDEPENDENT CURRENT REFERENCE 失效
    温度独立电源参考

    公开(公告)号：EP0927385A4

    公开(公告)日：2000-08-23

    申请号：EP98918945

    申请日：1998-05-04

    申请人： MOTOROLA INC

    发明人： CZARNOCKI WALTER

    IPC分类号： G05F3/24 ,  G05F3/16

    CPC分类号： G05F3/242

    摘要： A current reference (10) includes first and second connected resistors (R1 and R2), a voltage source (12) independent of a supply voltage (Vdd). The voltage source is applied to the first and second resistors (R1 and R2) and has a positive temperature coefficient (TC). The first resistor (R1) has a TC less than the voltage source (12) TC and the second resistor (R2) has a TC greater than the voltage source (12) TC. A resistance value of each of the first and second resistors is set such that a combined TC of the first and second resistors is essentially equal to the voltage source (12) TC such that the current reference (10) produces a current essentially independent of a temperature of the current reference (10) and the supply voltage (Vdd).