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    EFFICIENT AND PRECISE EVENT SCHEDULING FOR IMPROVED NETWORK PERFORMANCE, CHIP RELIABILITY AND REPARABILITY
    3.
    发明公开
    EFFICIENT AND PRECISE EVENT SCHEDULING FOR IMPROVED NETWORK PERFORMANCE, CHIP RELIABILITY AND REPARABILITY 审中-公开

    公开(公告)号：EP4220420A1

    公开(公告)日：2023-08-02

    申请号：EP22210098.4

    申请日：2022-11-29

    申请人： Avago Technologies International Sales Pte. Limited

    发明人： KADU, Sachin Prabhakarrao

    IPC分类号： G06F13/362 ,  H04L47/50

    摘要： Disclosed herein are related to systems and methods for scheduling network operations with synchronized idle slots. In one aspect, a system includes a first data path to provide a first set of packets and a second data path to provide a second set of packets. The system also includes an arbiter to arbitrate the first set of packets and the second set of packets. The arbiter may be configured to receive a request for a task, where the task may be performed during a clock cycle. Based on the request, the arbiter may cause a scheduler to schedule a first idle slot for the first data path, and schedule a second idle slot for the second data path. The arbiter may provide the first idle slot and the second idle slot.

    SEMICONDUCTOR DEVICE WITH MASTER, BUS, CACHE AND MEMORY CONTROLLER AND BUS GENERATOR
    5.
    发明公开
    SEMICONDUCTOR DEVICE WITH MASTER, BUS, CACHE AND MEMORY CONTROLLER AND BUS GENERATOR 审中-公开

    公开(公告)号：EP3872644A1

    公开(公告)日：2021-09-01

    申请号：EP21164812.6

    申请日：2018-12-20

    申请人： Renesas Electronics Corporation

    发明人： Yamanaka, Sho ,  Hiraki, Toshiyuki ,  Honda, Nobuhiko

    IPC分类号： G06F13/16 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0804 ,  G06F13/362 ,  G06F13/40

    摘要： A master issues a write request and a read request. A memory controller includes a request buffer for storing the write and read request, and accesses a memory in accordance with the stored write and read request. A cache is arranged between the master and the memory controller. A first write request issue control unit is arranged in correspondence with a first write request bus coupling the first master and the cache. A second write request issue control unit is arranged in correspondence with a second write request bus coupling the cache and the memory controller. First and second central bus control systems grant an access right to the first and second write request issue control units in accordance with a free situation of the cache and a fee situation of the request buffer, respectively. A read request issue control unit arranged in a manner corresponding to a read request bus, the second central bus control system configured to, using said read request issue control unit, control output of the read request issued by the first master to the memory controller in accordance with a free situation of the request buffer. The first write request issue control unit receives the write request issued from the master, and outputs the received write request in response to granting of the access right from the first central bus control system. The cache caches the write request output from the first write request issue control unit. The second write request issue control unit receives the write request from the cache, and outputs the received write request to the memory controller in response to granting of the access right from the second central bus control system.

    SEMICONDUCTOR DEVICE AND ACCESS CONTROL METHOD
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND ACCESS CONTROL METHOD 审中-公开

    公开(公告)号：EP3872643A1

    公开(公告)日：2021-09-01

    申请号：EP21164807.6

    申请日：2018-06-20

    申请人： Renesas Electronics Corporation

    发明人： Mizumoto, Katsuya ,  Hiraki, Toshiyuki ,  Honda, Nobuhiko ,  Yamanaka, Sho ,  Irita, Takahiro ,  Hotta, Yoshihiko

    IPC分类号： G06F13/16 ,  G06F13/18 ,  G06F13/362

    摘要： Access control is achieved in consideration of write training. At least one master issues access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the mater. A central bus-control system controls the output of the access requests issued by the master to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the master.

    SERIAL PERIPHERAL INTERFACE MASTER
    9.
    发明公开
    SERIAL PERIPHERAL INTERFACE MASTER 审中-公开

    公开(公告)号：EP3709177A1

    公开(公告)日：2020-09-16

    申请号：EP19162494.9

    申请日：2019-03-13

    申请人： Axis AB

    发明人： Zander, Per ,  Wennersten, Johan

    IPC分类号： G06F13/362

    摘要： A Serial Peripheral Interface (SPI) master (110) and method therein for transferring data to a peripheral device in a data communication and processing system (100) are disclosed. The SPI master (110) comprises a memory (111) comprising a list of packets, each packet comprises data associated with a time parameter indicating at which time the data is to be transferred to the peripheral device. The time parameter is configurable. The SPI master further comprises a serial transmit and receive unit (112) to transfer the data in the list at a time according to the time parameter associated with the data.