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    IN-NETWORK COMPUTE OPERATIONS
    1.
    发明公开
    IN-NETWORK COMPUTE OPERATIONS 审中-公开

    公开(公告)号：EP4502783A1

    公开(公告)日：2025-02-05

    申请号：EP24184069.3

    申请日：2024-06-24

    Applicant: Intel Corporation

    Inventor： NAEIMI, Helia A. ,  FINGERHUT, John Andrew

    IPC: G06F7/483 ,  G06F15/173

    Abstract: Examples described herein relate to an interface and circuitry coupled to the interface, the circuitry configured to execute instructions that cause the circuitry to perform floating point (FP) operations based on floating point data received in different packets. The order of the floating point operations can be based on a reorder of the data received in the different packets and wherein the reorder of the data received in the different packets is different than the order in which the packets were received.

    HARDWARE EFFICIENT ROUNDING
    3.
    发明公开
    HARDWARE EFFICIENT ROUNDING 审中-公开

    公开(公告)号：EP4418103A1

    公开(公告)日：2024-08-21

    申请号：EP24157311.2

    申请日：2024-02-13

    Applicant: Imagination Technologies Limited

    Inventor： King, Rostam ,  Fenney, Simon

    IPC: G06F7/483 ,  G06F7/499

    CPC classification number: G06F7/49947 ,  G06F7/4836

    Abstract: A binary logic circuit and method are disclosed for rounding an unsigned normalised n-bit binary number to an m-bit binary number. A correction value of length of n bits and a pre-truncation value of length of n bits are determined. The correction value is determined by shifting the n-bit number by m bits. The pre-truncation value is determined based on at least the n-bit number, the correction value, a value for the most significant bit (MSB) of the n-bit number, and a rounding value having a '1' at the n-mth bit position and a '0' at all other bits. The rounded m-bit number is then obtained by truncating the n-m least significant bits (LSB) of the pre-truncation value.

    CALCULATION UNIT FOR MULTIPLICATION AND ACCUMULATION OPERATIONS
    6.
    发明公开
    CALCULATION UNIT FOR MULTIPLICATION AND ACCUMULATION OPERATIONS 审中-公开

    公开(公告)号：EP4336344A1

    公开(公告)日：2024-03-13

    申请号：EP23191884.8

    申请日：2023-08-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： GANDOLFI, Luca ,  GAROZZO, Ugo

    IPC: G06F7/483 ,  G06F7/544

    Abstract: A calculation unit includes: a multiplier (16), configured to calculate a product (w ij x j ) of a first factor (w ij ) and a second factor (x j ); an accumulation memory element (18), containing a current accumulation value (ACC j ); and a floating-point sum/subtraction unit (17), coupled to the multiplier (16; 116) and the accumulation memory element (18) to receive respectively the product (w ij x j ) and the current accumulation value (ACC j ) and configured to calculate an updated accumulation value (ACC j+1 ) based on the sum of the product (w ij x j ) and the current accumulation value (ACC j ) and to store the updated accumulation value (ACC j+1 ) in the accumulation memory element (18). The first factor (w ij ) and the second factor (x j ) each comprise a respective sign bit (SGN(w ij ), SGN(x j )) and respective exponent bits (EXP(w ij )).

    COMPUTER-IMPLEMENTED METHOD FOR TRANSFORMING A BIT STREAM INTO A FLOATING POINT NUMBER
    7.
    发明公开
    COMPUTER-IMPLEMENTED METHOD FOR TRANSFORMING A BIT STREAM INTO A FLOATING POINT NUMBER 审中-公开

    公开(公告)号：EP4310666A1

    公开(公告)日：2024-01-24

    申请号：EP22382683.5

    申请日：2022-07-18

    Applicant: Quside Technologies S.L.

    Inventor： Ramón Martínez Saavedra, José ,  Abellán Sánchez, Carlos

    IPC: G06F7/483 ,  G06F7/58

    Abstract: Computer-implemented method comprising obtaining a bit stream and transforming the bit stream into a floating-point number, wherein the floating-point number comprises an exponent and a significand, the transformation comprising determining the exponent of the floating-point number based on counting a number of bitwise shifts needed to obtain a bit value of 1 at a designated position of the bit stream, the transformation further comprising determining the significand of the floating-point number based on a certain number of bits that are different from the bits used for determining the exponent.

    METHOD AND SYSTEM FOR CALCULATING DOT PRODUCTS
    9.
    发明公开
    METHOD AND SYSTEM FOR CALCULATING DOT PRODUCTS 审中-公开

    公开(公告)号：EP4231134A1

    公开(公告)日：2023-08-23

    申请号：EP23155921.2

    申请日：2023-02-09

    Applicant: Imagination Technologies Limited

    Inventor： Ferrere, Thomas

    IPC: G06F7/483 ,  G06F7/544

    Abstract: A method of performing dot product of an array of '2k' floating point numbers comprising two sets of k floating-point numbers a i and b i is disclosed. The method includes receiving both sets of 'k' floating point numbers and multiplying each floating point number a i with a floating point number b i to generate k product numbers (z i ), each product number (z i ) having a mantissa bit length of 'r+ log (k-1) +1' bits. The method further comprises creating a set of 'k' numbers (y i ) based on the k product numbers (z i ), the numbers (y i ) having a bit-length of 'n' bits. Further the method includes identifying a maximum exponent sum (e max ) among k exponent sums (eab i ) of each pair of floating point numbers a i and b i , aligning the magnitude bits of the numbers (y i ) based on the maximum exponent sum (e max ) and adding the set of 'k' numbers concurrently to obtain the dot product.

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