摘要:
Disclosed is an accelerator which includes a first to a K-th stage performing an NTT (Number Theoretic Transform) operation of first input data including a polynomial of a homomorphic ciphertext, the first to K-th stages being connected in series, and a first assist circuit generating a first to a K-th enable signal based on a degree of the polynomial of the first input data. Each of the first to K-th stages performs a butterfly operation of the first input data or corresponding output data of a previous stage in response to that the corresponding enable signal among the first to K-th enable signals indicates a first logical value, and bypasses the first input data or the corresponding output data of the previous stage in response to that the corresponding enable signal among the first to K-th enable signals indicates a second logical value.
摘要:
Circuits and associated methods are disclosed, for processing two floating-point numbers (A, B) to generate a sum (A+B) of the two numbers and a difference (A-B) of the two numbers. The method comprises calculating (806) a sum (|A|+|B|) of the absolute values of the two floating-point numbers, using a same-sign floating-point adder (1020), to produce a first result. The method further comprises calculating (808) a difference (|A|-|B|) of the absolute values to produce a second result. The sum (A+B) and the difference (A-B) are generated (810, 812) based on the first result (|A|+|B|), the second result (|A|-|B|), and the sign of each floating-point number.
摘要:
A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out.
摘要:
This disclosure describes techniques for determining a shape of a signal. In particular, a kernel is applied to a portion of a signal to compute at least a first, first order derivative of the portion of the signal and a second, first order derivative of the portion of the signal in a single pass of the kernel. The shape of the portion of the signal is determined based on the first and second first order derivatives. In one example, the shape of the portion of the signal is determined based on the ratio of the first, first order derivative and the second, first order derivative. These techniques may be particularly effective for detecting edges within image signals. However, the techniques may be used to detect the shape of significant changes within any signal that represents a variable that is changing over time, space or other dimension.
摘要:
A computer system that makes it difficult to analyze the content of a calculation. A power operation unit (262) performs the following operations using the input data "a" and "b": g a = g a mod n, g b = g b mod n. Next, a multiplication unit (264) performs the following calculation using g a and g b : g ab = g a × g b mod n. Next, a discrete logarithm calculation unit (266) calculates c i mod p i - 1 to satisfy g ab = g ci mod p i (i = 1, 2, 3,...,k). Next, a CRT unit (267) calculates "c" to satisfy c i = c mod p i - 1 (i = 1, 2, 3,...,k) using the Chinese remainder theorem CRT.
摘要翻译:使计算机系统内容难以分析的计算机系统。 电力操作单元(262)使用输入数据“a”和“b”执行以下操作:g a = g a mod n,g b = g b mod n。 接下来,乘法单元(264)使用g a和g b执行以下计算:g ab = g a×g b mod n。 接下来,离散对数计算单元(266)计算c i mod p i-1以满足g ab = g ci mod p i(i = 1,2,3,...,k)。 接下来,CRT单元(267)使用中文余数定理CRT来计算“c”以满足c i = c mod p i-1(i = 1,2,3,...,k)。