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公开(公告)号：EP2446535B1
公开(公告)日：2017-04-19
申请号：EP10730946.0
申请日：2010-06-28
CPC分类号： H03K5/1565 , H03K21/38 , H03K23/00
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3.发明公开Digital counter comprising reduced transition density 审中-公开DigitalersZählermit reduzierter Transitionsdichte
公开(公告)号：EP2899887A1
公开(公告)日：2015-07-29
申请号：EP14152342.3
申请日：2014-01-23
发明人： Dahan, Nir
CPC分类号： H03K23/005 , H03K23/40 , H03K23/50 , H03K23/542 , H03K23/588
摘要： The present document relates to a digital counter (100) providing counting information comprising:
- at least a first and a second counting module (110a, 110b), said counting modules (110a, 110b) being serially coupled forming a counting module chain;
- each counting module (110a, 110b) comprising at least a first and a second digital storage cell (111, 112), each counting module (110a, 110b) providing module counting information comprising a width of at least two bits;
- the counting modules (110a, 110b) being adapted to change only one bit of said module counting information between two successive counting states;
wherein the counting modules (110a, 110b) are coupled such that the start of counting of the second counting module (110b) is triggered by the first counting module (110a) if said first counting module (110a) once has passed through its possible counting states.摘要翻译： 本文件涉及提供计数信息的数字计数器（100），包括： - 至少第一和第二计数模块（110a，110b），所述计数模块（110a，110b）串联耦合形成计数模块链; - 每个计数模块（110a，110b）包括至少第一和第二数字存储单元（111,112），每个计数模块（110a，110b）提供包括至少两个比特的宽度的模块计数信息; - 计数模块（110a，110b）适于在两个连续计数状态之间仅改变所述模块计数信息的一位; 其中所述计数模块（110a，110b）被耦合，使得如果所述第一计数模块（110a）曾经通过其可能的计数，则由所述第一计数模块（110a）触发所述第二计数模块（110b）的开始计数 状态。
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公开(公告)号：EP2509225A3
公开(公告)日：2013-04-10
申请号：EP12004501.8
申请日：2007-06-27
发明人： Narathong, Chiewcharn , Su, Wenjun
CPC分类号： H03K23/54
摘要： A modulus divider stage (MDS) includes first and second stages. The MDS receives a modulus divisor control signal S that determines whether the MDS stage operates in a divide-by-two mode or a divide-by-three mode. The MDS stage also receives a feedback modulus control signal from another MDS. When in the divide-by-two mode, the MDS divides by two regardless of the feedback modulus control signal. To conserve power, the first stage is unpowered when the MDS stage operates in the divide-by-two mode. When in the divide-by-three mode, the MDS stage either divides by two or by three depending on the feedback modulus control signal. To further reduce power consumption, the first stage is unpowered when the MDS stage is in the divide-by-three mode but is nonetheless performing a divide-by-two operation. A power-down transistor holds the output of the first stage at the proper logic level when the first stage is unpowered.
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5.发明授权NON-POWER-OF-TWO GRAY-CODE COUNTER SYSTEM HAVING BINARY INCREMENTER WITH COUNTS DISTRIBUTED WITH BILATERAL SYMMETRY 有权并非在两个POTENZ BASED格雷码计数器与二进制INCREMENTIERER两制双面对称分布号码
公开(公告)号：EP1410509B1
公开(公告)日：2008-09-10
申请号：EP01978284.6
申请日：2001-08-17
申请人： NXP B.V.
发明人： PONTIUS, Timothy, A.
IPC分类号： H03K23/00
CPC分类号： G06F5/14 , G06F2205/102 , G06F2205/106 , H03K23/005
摘要： A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide 'full' and 'empty' indications. When read and write counts differ at the two most-significant bit positions but are equal at the remaining bit positions, the detector provides a 'full' indication for a 6-count FIFO. The gray-code counter design is scaleable to any non-power-of-two modulo number divisible by four.
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公开(公告)号：EP1405417A1
公开(公告)日：2004-04-07
申请号：EP01950112.1
申请日：2001-07-06
摘要： A frequency divider device including: a divider input: a phase count and select section including: at least two phase count and select inputs each communicatively connected to the divider input, for receiving each at least one phase shifted signal having a phase difference with respect to the other phase shifted signal; a signal generator section for generating an output signal; a switch device having switch inputs each connected to said at least one of said phase count and select inputs, said switch device further having at least one switch output, said switch device connecting a selected input of said switch inputs with said switch output, an inverter device for switching said output signal from a current state to a substantially inverse state if a selected signal from a current state to a substantially inverse state if a selected signal from said selected input has a transition from a first state to s a second state; a counter device for determining a number of periods of said selected signal; a switch actuator device for switching said switch device to another one of said switch inputs if a value of said counter device has reached a preset switching value; and a divider output.
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公开(公告)号：EP1065787A3
公开(公告)日：2001-01-24
申请号：EP00112902.2
申请日：2000-06-19
发明人： Hölzle, Josef
摘要： Die Erfindung betrifft ein Verfahren, sowie eine Schaltungsanordnung zum Hochgeschwindigkeitszählen von Taktzyklen eines Taktes, der in einem ersten Schritt in einem Verhaltnis 1 zu n geteilt wird, dessen Zyklen von einer Zähleinheit (7) gezählt werden, wobei diese Zähleinheit (7) pro Taktzyklus n Schritte zählt, die Taktzyklen des geteilten Taktes hinsichtlich eines Wertes 0 bis n-1 analysiert werden und bei einem Auftreten eines Wertes 0 bis n-1 in dessen Abhängigkeit eine Verzögerung eines Signals erzeugt und ausgegeben wird.
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8.发明授权Frequency divider, frequency measurement circuit and pulse generator using a common delay circuit 失效频率测量和脉冲发生器与一个共同的延迟电路分频电路
公开(公告)号：EP0660518B1
公开(公告)日：1999-06-09
申请号：EP94120564.3
申请日：1994-12-23
申请人： DENSO CORPORATION
CPC分类号： H03K3/0315 , H03K5/135
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9.发明授权Image pickup apparatus and counter circuit used therein 失效Bildaufnahmegerätmit darin verwendeterZählerschaltung
公开(公告)号：EP0456193B1
公开(公告)日：1999-01-20
申请号：EP91107415.1
申请日：1991-05-07
发明人： Hachiyama, Hiroki , Iwasawa, Takahiro , Ohmae, Masanori , Yoshida, Masakatsu , Hatano, Toshinobu , Tsuji, Masakazu
CPC分类号： H03K23/005 , H04N5/067 , H04N5/335 , H04N5/372 , H04N5/3765
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公开(公告)号：EP0821485A3
公开(公告)日：1998-03-18
申请号：EP97301559.7
申请日：1997-03-10
发明人： Shona, Yoshihiro
IPC分类号： H03K23/00
CPC分类号： H03K21/403 , H03K23/005
摘要： A call-unit count device according to the present invention comprises a memory circuit having a high-order level and a low-order level composed of n (n: integer greater than or equal to 2) bits and wherein all the bits each indicative of the initial value and placed in the low-order level are changed to reversed values bit by bit each time a one call-unit add command is given, all the bits in the low-order level, which have been brought to the reversed values, are returned to the initial value bit by bit each time the one call-unit add command is given, and values stored in the high-order level are changed upon a carry from the low-order level to the high-order level.
摘要翻译： 根据本发明的呼叫单元计数设备包括具有由n（n是大于或等于2的整数）个比特组成的高阶电平和低阶电平的存储器电路，并且其中所有比特均指示 每次给出一个呼叫单元添加命令时，将初始值和置于低阶电平的初始值逐位改变为反转值，低阶电平中的所有位都被置为反转值， 在每次给出一个呼叫单元添加命令时逐位地返回到初始值，并且在从低位级到高级级的进位时改变存储在高位级的值。
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