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    Input/output interface and semiconductor integrated circuit having input/output interface
    3.
    发明公开
    Input/output interface and semiconductor integrated circuit having input/output interface 有权
    输入/输出接口，以及与输入/输出接口的半导体集成电路

    公开(公告)号：EP1286470A3

    公开(公告)日：2004-06-23

    申请号：EP01310174.6

    申请日：2001-12-05

    申请人： FUJITSU LIMITED

    发明人： Matsuzaki, Yasurou, c/o Fujitsu Limited

    IPC分类号： H03M5/02

    CPC分类号： H04L25/493 ,  H03M5/02

    摘要： An input/output interface is provided in which a logical value is expressed by an order that transition edges appear in a plurality of transmission signals transmitting respectively on a plurality of signal lines (DA, DB, DC, DD). Otherwise, the logical value is expressed by a time difference between the transition edge of the transmission signal transmitting on the signal line and a transition edge of a standard timing signal. Therefore, a large amount of data can be transmitted through one signal line. Since a large amount of data can be transmitted by one transmission, it is possible to substantially increase the data transfer rate. Since only a small number of the signal lines are necessary, it is possible to reduce the number of input circuits and output circuits of the transmission signals, to reduce power consumption, and to reduce the wiring area of the signal lines.

    IMPROVED DECODER CIRCUIT
    4.
    发明授权
    IMPROVED DECODER CIRCUIT 失效
    改进的解码器电路

    公开(公告)号：EP0489819B1

    公开(公告)日：1993-03-31

    申请号：EP90913305.0

    申请日：1990-08-23

    申请人： EASTMAN KODAK COMPANY

    发明人： SILVA, Fernando, Goncalves

    IPC分类号： G11B20/14 ,  H03M5/02

    CPC分类号： H03M5/14 ,  H03M5/12

    摘要： An improved decoder circuit suitable for decoding an encoded binary data stream. The encoding is expected to generate a three-part code format, the format, in turn, comprising a pair of clock transitions that set-off a data transition. The improved decoder circuit establishes whether or not the expected format is in fact realized under arbitrary operating conditions, and in the event of a failure to realize the expected format, provides a suitable format for a subsequent decoding procedure.

    DATA COMPRESSION METHOD, AND REDUCTION METHOD, DEVICE AND SYSTEM
    5.
    发明公开
    DATA COMPRESSION METHOD, AND REDUCTION METHOD, DEVICE AND SYSTEM 审中-公开
    数据压缩方法和还原法，设备及系统

    公开(公告)号：EP2953303A4

    公开(公告)日：2016-04-20

    申请号：EP13877388

    申请日：2013-03-07

    申请人： HUAWEI TECH CO LTD

    发明人： QIN FENGPING

    IPC分类号： H04L25/02 ,  H03M5/02 ,  H03M7/30 ,  H04B1/66 ,  H04L25/03 ,  H04L25/08

    CPC分类号： H04B1/66 ,  H03M5/02 ,  H03M7/30 ,  H03M7/3059 ,  H04L25/03159 ,  H04L25/08

    摘要： The present invention relates to a data compression method, a data restoration method, apparatuses, and a system. The data compression method includes: acquiring a first digital signal; acquiring a first compressed signal by performing down-sampling processing on the first digital signal, where a sampling frequency of the first compressed signal is not less than a frequency threshold, and the frequency threshold is twice a baseband cut-off frequency of the first digital signal; and sending the first compressed signal by using a transmission format based on the common public radio interface CPRI protocol. Frequency decrease is performed before data is transmitted by using the CPRI protocol, so as to reduce an amount of data to be transmitted by using a CPRI, and improve data transmission efficiency, or, in other words, increase a quantity of RRUs or BBUs that can be supported on per CPRI.

    CODING OF INFORMATION IN INTEGRATED CIRCUITS
    7.
    发明授权
    CODING OF INFORMATION IN INTEGRATED CIRCUITS 有权
    信息的集成电路CODING

    公开(公告)号：EP1540828B1

    公开(公告)日：2009-02-25

    申请号：EP03795107.6

    申请日：2003-08-06

    申请人： NXP B.V.

    发明人： PESSOLANO, Francesco ,  VAN DIJK, Victor, E., S.

    IPC分类号： H03M5/02

    CPC分类号： H04L25/0266 ,  G01R31/318538 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a method for coding information in an electronic circuit and an electronic circuit for coding information, said circuit comprising at least two electrically coupled signal paths (X0, X1). The invention is based on the idea that cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first path (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0), an output signal (X) having a second logic value is produced.

    Method for modulating a binary data stream
    9.
    发明公开
    Method for modulating a binary data stream 失效
    Verfahren zum Modulieren einesbinärenDatenstromes。

    公开(公告)号：EP0346775A1

    公开(公告)日：1989-12-20

    申请号：EP89110494.5

    申请日：1989-06-09

    申请人： EASTMAN KODAK COMPANY (a New Jersey corporation)

    发明人： Wash, Michael Lee c/o EASTMAN KODAK COMPANY

    IPC分类号： G11B20/14 ,  H03M5/02

    CPC分类号： H03M5/12

    摘要： A method for modulating a binary data stream into a code format suitable for encoding information that employs a non-return-to-zero (NRZ) technique. The method consisting in: (1) defining a bitcell as the time t between two adjacent clock transitions; (2) writing a first clock transition at the beginning of the bitcell; and (3) encoding a binary data transition in the ratio of td/t, where td is the time duration between the first clock tansition and the data transition, with the proviso that td/t ≠ 1/2. Preferably, the ratio td/t 1/2 encodes a data 1 bit. The method is specially advantageously employed where the information transfer rate is dependent on unpredicable and variable transfer rate velocities and accelerations.

    摘要翻译： 一种用于将二进制数据流调制成适于编码采用非归零（NRZ）技术的信息的编码格式的方法。 该方法包括：（1）将位元定义为两个相邻时钟转换之间的时间t; （2）在比特单元的开头写入第一时钟转换; 和（3）以td / t的比率对二进制数据转换进行编码，其中td是第一时钟转换和数据转换之间的持续时间，条件是td / t NOTEQUAL 1/2。 优选地，比率td / t <1/2对数据0位进行编码，并且比例td / t> 1/2对数据1位进行编码。 该方法特别有利地用于信息传递速率取决于不可预测和可变的传输速率速度和加速度。