CLOCK AND DATA RECOVERY
    2.
    发明公开

    公开(公告)号:EP4507244A1

    公开(公告)日:2025-02-12

    申请号:EP23191118.1

    申请日:2023-08-11

    Inventor: VERBEKE, Marijn

    Abstract: Example embodiments describe a method and a circuitry to perform clock and data recovery, CDR. The method comprises the steps of obtaining an analogue communication signal characterized by a symbol frequency F symbol ; performing an analogue-to-digital conversion of the analogue communication signal according to a sampling rate F sample targeting F symbol *(M/L) thereby obtaining a digital signal; up-sampling the digital signal by L; filtering the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; down-sampling the filtered digital signal by M resulting in a recovered digital signal; obtaining intermediate filter coefficients for the FIR filter; determining a phase error based on the recovered digital signal; interpolating the intermediate filter coefficients based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients; and updating the filter coefficients of the FIR filter with the interpolated filter coefficients.

    INFORMATION MEASUREMENT METHOD AND APPARATUS

    公开(公告)号:EP4436124A1

    公开(公告)日:2024-09-25

    申请号:EP22906019.9

    申请日:2022-10-09

    CPC classification number: H04L43/0852 H04L7/00

    Abstract: Provided are an information measurement method and apparatus. The information measurement method includes: receiving, by a second network device, a cycle offset measurement message sent by a first network device adjacent to the second network device at a starting moment of a scheduling cycle, wherein the cycle offset measurement message comprises a field representing a cycle length of the scheduling cycle; and determining, by the second network device, a cycle offset of the scheduling cycle between the first network device and the second network device according to a receiving moment at which the second network device receives the cycle offset measurement message, the cycle length of the scheduling cycle, and a link latency between the first network device and the second network device. By means of the embodiments of the present disclosure, a scheduling cycle offset between network devices can be measured and acquired, and necessary information can be provided for accurate calculation and planning of a service with a low latency and low jitter requirement, thereby effectively improving a utilization rate of network resources.

    FORWARDING DEVICE AND TIME SYNCHRONIZATION SYSTEM

    公开(公告)号:EP4418602A1

    公开(公告)日:2024-08-21

    申请号:EP21967269.8

    申请日:2021-12-10

    CPC classification number: H04J3/0667 H04J3/0641

    Abstract: A transfer apparatus (10) includes a Pdelay message reception process (101), a Sync/Follow up message reception process (102), an Announce message reception process (103), a Sync reception/transmission guard management process (104), a delay measurement arithmetic process (105), a time synchronization arithmetic process (106), a time selection arithmetic process (107), and a frame transmission process (108). The transfer apparatus (10) monitors a reception state of an Announce message (61) that notifies of time source information for each port, and in a case where, based on monitoring, a state of a time source worsened as in when reliability of time is reduced and the like, a Sync/Follow_up message (51) for time synchronization is made so as not to be transferred. By the above, the transfer apparatus (10) makes a time out of the Sync/Follow_up message (51) occur and worsening of the time source is notified to a different apparatus at high speed.

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