公开(公告)号：EP4436045A1

公开(公告)日：2024-09-25

申请号：EP24164929.2

申请日：2024-03-20

申请人： Samsung Electronics Co., Ltd.

发明人： LEE, Jaeyoung ,  KIM, Byungsu ,  KIM, Youngsan ,  LEE, Jaegon ,  KIM, Jaehoon ,  LEE, Byeongho ,  LEE, Jongjin ,  JEONG, Wookyeong

IPC分类号： H03K19/00 ,  G06F1/10 ,  G06F1/3237

CPC分类号： H03K19/0016 ,  G06F1/10 ,  G06F1/3237

摘要： A semiconductor device (1) includes an intellectual property (IP) block (140) configured to operate based on a first clock signal (CLK_OUT) and a power voltage (VDDin), a clock gating circuit (130) configured to operate based on the power voltage, and generate the first clock signal (CLK_OUT) by selectively performing clock gating on a second clock signal (CLK_IN) based on an enable signal (En), and a critical path monitor (CPM, 120) configured to generate a digital code (CPM code) having a value, which varies according to a voltage drop of the power voltage (VDDin), and activate the enable signal (En) based on a comparison of the value of the digital code with a reference value.

公开(公告)号：EP3928181B1

公开(公告)日：2024-09-18

申请号：EP19735072.1

申请日：2019-06-17

IPC分类号： G06F1/3231 ,  G06F3/01 ,  G06F1/3237 ,  G01S13/88 ,  G01S13/04 ,  G01S7/41 ,  G01S13/42

CPC分类号： G06F3/017 ,  G06F1/3231 ,  G06F1/3237 ,  G01S13/88 ,  G01S7/415 ,  G01S13/42 ,  Y02D30/50

公开(公告)号：EP4354250A1

公开(公告)日：2024-04-17

申请号：EP22201654.5

申请日：2022-10-14

申请人： EM Microelectronic-Marin SA

发明人： Ovidiu, SIMA

IPC分类号： G06F1/04 ,  G06F1/10 ,  G06F1/3237

CPC分类号： G06F1/10 ,  G06F1/04 ,  G06F1/3237

摘要： The present disclosure relates to a clock distribution network (10), comprising:
- a clock generator (14) configured to generate at least a processor clock signal and at least a first peripheral clock signal, the clock generator (14) further comprises at least a processor clock output (31), a first peripheral clock output (32) and a first clock request input (42),
- a processing unit (16) connected to the processor clock output (31) and configured to operate on a rising edge of the processor clock signal receivable via the processor clock output (31),
- at least a first peripheral unit (22) connected to the first peripheral clock output (32) and connected to the first clock request input (42) of the clock generator (14), wherein the at least first peripheral unit (22) is configured to operate on a falling edge of the first peripheral clock signal received via the first peripheral clock output (32),
- wherein the at least first peripheral unit (22) via the first clock request input (42) is operable to trigger the clock generator (14) to transmit the first peripheral clock signal via the first peripheral clock output (32).

公开(公告)号：EP3436897A1

公开(公告)日：2019-02-06

申请号：EP17720341.1

申请日：2017-04-13

申请人： Qualcomm Incorporated

发明人： WINEMILLER, Chad, Everett ,  BOYETTE, Jon, Raymond ,  DEANS, Russell, Coleman ,  ZHU, Zhi

IPC分类号： G06F1/32

CPC分类号： G06F1/3278 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D50/20

摘要： Power saving systems and methods for Universal Serial Bus (USB) systems are disclosed. When a USB physical layer (PHY) enters a U3 low power state, not only are normal elements powered down, but also circuitry within the USB PHY associated with detection of a low frequency periodic signal (LFPS) wake up signal is powered down. A low speed reference clock signal is still received by the USB PHY, and a medium speed clock within the USB PHY is activated once per period of the low speed reference clock signal. The medium speed clock activates the signal detection circuitry and samples a line for the LFPS. If no LFPS is detected, the signal detection circuitry and the medium speed clock return to low power until the next period of the low speed reference clock signal. If the LFPS is detected, the USB PHY returns to a U0 active power state.

公开(公告)号：EP1785811B1

公开(公告)日：2018-12-05

申请号：EP05292417.2

申请日：2005-11-14

申请人： Texas Instruments Incorporated ,  TEXAS INSTRUMENTS FRANCE

发明人： Dubost, Gilles ,  Dahan, Franck ,  Seigneret, Franck

IPC分类号： G06F1/32 ,  G06F13/28

CPC分类号： G06F1/3228 ,  G06F1/3215 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller (200) coupled to a memory storage device (245) and a peripheral device (240). The DMA controller transfers information from the memory storage device to a buffer (290) in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.

公开(公告)号：EP3340011A1

公开(公告)日：2018-06-27

申请号：EP17184172.9

申请日：2017-08-01

申请人： Samsung Electronics Co., Ltd.

发明人： MOON, Dong-uk

IPC分类号： G06F1/32

CPC分类号： G06F5/14 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0831 ,  G06F12/0875 ,  G06F2205/126 ,  G06F2212/621 ,  Y02D10/128 ,  Y02D10/152

摘要： An electronic device according to some example embodiments includes a clock management circuit (210) configured to control a clock signal (CLK) and a processor circuit (220) directly connected to the clock management circuit (210) and configured to provide a clock control request for the clock signal (CLK) to the clock management circuit (210) according to an operation status of the processor circuit (220).

公开(公告)号：EP3332307A1

公开(公告)日：2018-06-13

申请号：EP16744978.4

申请日：2016-07-05

申请人： Qualcomm Incorporated

发明人： PAL, Dipti Ranjan

IPC分类号： G06F1/32 ,  G06F1/08

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152

摘要： Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

公开(公告)号：EP3329345A1

公开(公告)日：2018-06-06

申请号：EP16830980.5

申请日：2016-06-14

申请人： Intel Corporation

发明人： GENDLER, Alexander ,  NOVAKOVSKY, Larisa ,  SISTLA, Krishnakanth V. ,  GARG, Vivek ,  MULLA, Dean ,  CHOUBAL, Ashish V. ,  HALLNOR, Erik G. ,  WEIER, Kimberly C.

IPC分类号： G06F1/32 ,  G06F13/14 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

摘要： In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

公开(公告)号：EP3256926A1

公开(公告)日：2017-12-20

申请号：EP16705327.1

申请日：2016-01-06

申请人： Qualcomm Incorporated

发明人： KOOB, Christopher Edward ,  CHEN, Xufeng ,  LESTER, Robert Allan ,  PYLA, Manojkumar ,  ZHONG, Peixin

IPC分类号： G06F1/32 ,  H03K19/00

CPC分类号： G06F1/26 ,  G06F1/3237 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/128 ,  Y02D10/171

摘要： The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

公开(公告)号：EP3213189A1

公开(公告)日：2017-09-06

申请号：EP15855579.7

申请日：2015-10-29

申请人： Spondoolies Tech Ltd.

发明人： GILBOA, Assaf ,  SHTEINGART, Zvi ,  LEVIN, Kobi ,  COREM, Guy

IPC分类号： G06F9/38 ,  G06F17/10 ,  H04L9/28 ,  G06Q20/06 ,  G06Q20/36 ,  G06Q20/38

CPC分类号： G06F1/3287 ,  G06F1/3237 ,  G06F1/324 ,  G06Q20/06 ,  G06Q20/065 ,  G06Q20/36 ,  G06Q20/3672 ,  G06Q20/38 ,  H04L9/0643 ,  H04L2209/125

摘要： A method and engine for hash calculation, the method comprising receiving data blocks via an input module, providing clock cycles by a clock module, calculating a hash from a received data block by a process module including a data pipeline and a state pipeline, the hash calculation comprising: an input data block to the data pipeline, the data block includes a sequence of data words including X data words, wherein X is a known number, calculating, in every other clock cycle of the clock module, an new data word based on the last calculated X data words, and performing a stage of the state pipeline in each clock cycle of the clock module, in which a state is calculated based on input from the data pipeline, the input includes the last calculated X data words, and outputting the hash via an output module every predetermined number of clock cycles.

摘要翻译： 一种用于散列计算的方法和引擎，所述方法包括经由输入模块接收数据块，由时钟模块提供时钟周期，由包括数据管道和状态管道的处理模块从接收的数据块计算散列，所述散列 计算包括：向数据流水线输入数据块，数据块包括包含X个数据字的数据字序列，其中X是已知数，在时钟模块的每隔一个时钟周期计算基于新数据字 在最后计算的X个数据字上，并且在时钟模块的每个时钟周期中执行状态管线的一个阶段，其中根据来自数据管线的输入计算状态，输入包括最后计算的X个数据字，以及 每隔预定数量的时钟周期经由输出模块输出散列。