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157 条记录 (耗时 0.013 秒)

    SUPERCONDUCTIVE INTEGRATED CIRCUIT CHIP
    52.
    发明专利
    SUPERCONDUCTIVE INTEGRATED CIRCUIT CHIP 失效

    公开(公告)号：JPS5712574A

    公开(公告)日：1982-01-22

    申请号：JP8662280

    申请日：1980-06-27

    申请人： HITACHI LTD

    发明人： HARADA YUTAKA ,  YAMASHITA KUNIO ,  KODERA NOBUO ,  TANAKA HIRONORI

    IPC分类号： H01L27/18 ,  H01L39/02 ,  H01L39/22 ,  H03K17/92

    摘要： PURPOSE:To facilitate standardization of buffer circuits of a chip and structure of pattern of a supercoductive integrated circuit chip by a method wherein input buffer circuits of an LSI are arranged at the neighborhood of pads, and wiring is facilitated without bringing superconductive conductors between the chips of the LSI in the chips, and the pads are provided in pairs. CONSTITUTION:The pairs of pads 109, 110 for drain and source are arranged systematically on the chip, and a group 50 of the input and output buffers 103, 102 consisted of switching circuits are made to be adjoined to a cell region 130. The pairs of pads are connected to the superconductive conductors 111, the superconductive conductors are connected magnetically to the input buffers 103, and the buffers 103 are driven with an input signal current. The wave form of the input signal is regulated, and the signal drives the prescribed cell in the region 130 through the superconductive conductor 115. Output of the output buffer 102 is outputted to the corresponding pad 110 through the wire 112, and nothing is connected to the pad 109. By this constitution, designing is made easy, and the superconductive IC chip having no mutual induction between the conductors and having no malfunction to be caused by noise can be obtained.

    54.
    发明专利
    失效

    公开(公告)号：JPS5633871B2

    公开(公告)日：1981-08-06

    申请号：JP15850275

    申请日：1975-12-31

    IPC分类号： H01L27/18 ,  H01L39/22 ,  H01L39/24

    JOSEPHSON CIRCUIT DEVICE
    55.
    发明专利
    JOSEPHSON CIRCUIT DEVICE 失效

    公开(公告)号：JPS55127089A

    公开(公告)日：1980-10-01

    申请号：JP3520579

    申请日：1979-03-26

    申请人： NIPPON TELEGRAPH & TELEPHONE

    发明人： ONODERA MASARU ,  ISHIDA AKIRA ,  YAMASHITA TSUTOMU

    IPC分类号： G11C11/44 ,  H01L27/18 ,  H01L39/22 ,  H03K17/92 ,  H03K19/195

    摘要： PURPOSE:To obtain a Josephson circuit wherein a superconductive closed circuit is formed by four or more Josephson junctions so that a predetermined function is achieved by making use of the characteristic that the fluxoid quantum is preserved without any inductance element. CONSTITUTION:Four or more Josephson junctions J1, J2...JN are connected successively to form a superconductive closed circuit M. The first current line 21 is derived from the neutral point A of connection between the junctions J1 and J2. Similarly, a second and third current lines 22 and 23 are derived from the neutral points B, C of connection between the junctions J2 and J3 and between the junctions J1, JN, respectively. In the first step of the operation, the circuit M is supplied with only the electric current IB through the lines 21, 23 at a value of a point P enclosed by curves 24, 25. Then, current IN is supplied at a value represented by a point Q which is outside the region of the curve 24 but within the region of the curve 25. As a result, such a state is created that only one fluoxid quantum resides in the circuit M. This quantum is extinguished when the values of the currents IB and IN are changed to that represented by a point R. The predetermined circuit function is thus obtained.

    ANALOGGDIGITAL CONVERTER USING JOSEPHSON ELEMENT
    56.
    发明专利
    ANALOGGDIGITAL CONVERTER USING JOSEPHSON ELEMENT 失效

    公开(公告)号：JPS54127668A

    公开(公告)日：1979-10-03

    申请号：JP3584078

    申请日：1978-03-28

    申请人： FUJITSU LTD

    发明人： HASUO SHINYA

    IPC分类号： H03M1/36 ,  H01L27/18 ,  H01L39/22

    摘要： PURPOSE:To obtain an A-D converter which features an extremely simple constitution with a low production cost by using the Josephson logic gate which can perform the unique operation. CONSTITUTION:The A-D converter shown in the diagram converters the analog signals of 0, I0, 2I0 ... 7I0 into the pure binary digital signals of 3 bits. Unit current I0 is set to a fixed value, and current adjustment resistance R0 limites the maximum analog signal within 7I0. The bias magnetic field is applied properly to each of the binary generation gates G1, G2 and G3 according to the critical current - external magnetic field characteristics. The presence or absence of the load current caused by current Ii is made to correspond to logic ''1'' and ''0'' respectively, and thus analog signal I can be converted into the pure binary digital signal of 3 bits. In case the output signal of the time series is required, the independent bias current source is prepared to each binary number generation gate, and then the current source is actuated in time series.

    FULL SUBTRACTOR USING JOSEPHSON LOGIC GATE
    57.
    发明专利
    FULL SUBTRACTOR USING JOSEPHSON LOGIC GATE 失效

    公开(公告)号：JPS54127645A

    公开(公告)日：1979-10-03

    申请号：JP3583878

    申请日：1978-03-28

    申请人： FUJITSU LTD

    发明人： SUZUKI HIDEO ,  HASUO SHINYA

    IPC分类号： G06F7/48 ,  G06F7/50 ,  G06F7/506 ,  H01L27/18 ,  H01L39/22

    摘要： PURPOSE:To simplify the constitution as well as to increase the operation speed by constituting the full sbtractor with the Josephson element. CONSTITUTION:The parallel subtractor device consists of borrow signal generators 1-1-1-N, differential pressure signal generators 2-1-2-N, borrow signal generator bias line 3, differential pressure signal generator bias line 4 and others. Generators 2-1-2-N is formed by the circuit comprising Josephson element J1 and J2, inductance L, bias current I and external magnetic field He. After flowing the bias current to line 3, minuends A1-AN and subtrahends B1-BN are supplied to produce the borrow signals successively from the lower ranked digits. Thus, the borrow signals are generated up to the N-th digit, and then the bias current is flowed to line 4 to generate the differential signals equivalent to N digits to be obtained. Here, if the borrow signal BN of the final digit is logic ''1'', A - B is negative due to A

    非線形マイクロ波フィルタ
    58.
    发明专利
    非線形マイクロ波フィルタ 审中-公开

    公开(公告)号：JPWO2020105732A1

    公开(公告)日：2021-10-14

    申请号：JP2019045772

    申请日：2019-11-22

    申请人： 国立研究開発法人科学技術振興機構

    发明人： 中村 泰信 ,  河野 信吾 ,  越野 和樹

    IPC分类号： H01L39/22 ,  H01L39/06 ,  H01P7/08 ,  H01P1/20 ,  H01L27/18

    摘要： 非線形マイクロ波フィルタは、超伝導量子回路において制御される量子ビットである標的量子ビットが形成される回路基板に形成されて、標的量子ビットが結合する制御用導波路に結合する量子ビットであり、制御用導波路における導波路端との距離が共鳴波長の半整数倍から所定の範囲内であり、標的量子ビットの共鳴周波数との差が所定の範囲内である共鳴周波数をもち、制御用導波路との結合が、標的量子ビットと制御用導波路との結合に比べて所定の値だけ大きい、量子ビットを備える。