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公开(公告)号：JP5299878B2
公开(公告)日：2013-09-25
申请号：JP2011231068
申请日：2011-10-20
Applicant: 国立大学法人静岡大学
Inventor： 祥二 川人
IPC: H03M1/14
CPC classification number: H03M1/144 , H03M1/0695 , H03M1/146
Abstract: A conversion operation B is performed with respect to a sample value R in an A/D conversion stage 101 to generate a conversion result D3, and a sampling operation A is performed with respect to this conversion result D3 in an A/D conversion stage 103. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 105 to generate a conversion result D4, and the sampling operation A is performed with respect to the conversion result D4 in an A/D conversion stage 107. The conversion operation B is performed with respect to a sample value in an A/D conversion stage 107 to generate a conversion result D5, and the sampling operation A is performed with respect to this conversion result D5 in an A/D conversion stage 101. The conversion operation B is performed with respect to a sample value in the A/D conversion stage 103 to generate a conversion result D6, and the sampling operation A is performed with respect to the conversion result D6 in the A/D conversion stage 105.
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3.发明专利Analog-digital converter and method for generating digital signal corresponding to analog signal 有权模拟数字转换器和数字信号生成与模拟信号相关的方法
公开(公告)号：JP2012016068A
公开(公告)日：2012-01-19
申请号：JP2011231045
申请日：2011-10-20
Applicant: National Univ Corp Shizuoka Univ , 国立大学法人静岡大学
Inventor： KAWAHITO SHOJI
IPC: H03M1/14
CPC classification number: H03M1/144 , H03M1/0695 , H03M1/146
Abstract: PROBLEM TO BE SOLVED: To provide an analog-digital converter that shortens A/D conversion time per one sampling.SOLUTION: A conversion operation B is performed with respect to a sample value R at an A/D conversion stage 101 to generate a conversion result D3, and a sampling operation A is performed with respect to the conversion result D3 at an A/D conversion stage 103. The conversion operation B is performed with respect to a sample value at an A/D conversion stage 105 to generate a conversion result D4, and the sampling operation A is performed with respect to the conversion result D4 at an A/D conversion stage 107. The conversion operation B is performed with respect to a sample value at an A/D conversion stage 107 to generate a conversion result D5, and the sampling operation A is performed with respect to the conversion result D5 at an A/D conversion stage 101. The conversion operation B is performed with respect to a sample value at the A/D conversion stage 103 to generate a conversion result D6, and the sampling operation A is performed with respect to the conversion result D6 at the A/D conversion stage 105.
Abstract translation: 要解决的问题：提供一个模拟数字转换器，可以缩短每次采样的A / D转换时间。 解决方案：相对于A / D转换级101处的采样值R执行转换操作B以产生转换结果D3，并且相对于A处的转换结果D3执行采样操作A / D转换级103.对于A / D转换级105的采样值执行转换操作B以产生转换结果D4，并且相对于A处的转换结果D4执行采样操作A / D转换级107.对于A / D转换级107的采样值执行转换操作B以产生转换结果D5，并且对A的转换结果D5进行采样操作A / D转换级101.对于A / D转换级103的采样值执行转换操作B以产生转换结果D6，并且针对A处的转换结果D6执行采样操作A / D转换阶段105.版权所有（C）2012，JPO＆INPIT
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公开(公告)号：JPWO2009088041A1
公开(公告)日：2011-05-26
申请号：JP2009548949
申请日：2009-01-08
Applicant: 国立大学法人静岡大学
IPC: H03M1/14
CPC classification number: H03M1/0602 , H03M1/0695 , H03M1/40
Abstract: 巡回型A/D変換器21は、複数のキャパシタ及び演算増幅器を共用して、複雑な処理を避けて増幅型ノイズキャンセル処理及び巡回型A/D変換を提供する。巡回型A/D変換器21では、ゲインステージ23は、第1〜第3のキャパシタ33、35、37及び演算増幅回路39を用いて、ノイズキャンセル処理及び増幅を行って第1及び第2の信号レベルの差分信号を生成する。ノイズキャンセル処理では、第1の信号レベルVRと第2の信号レベルVSとの差分が生成される。この差分の増幅は、ノイズキャンセル処理に伴って行われる。ゲインステージ23は、第1〜第3のキャパシタ33、35、37及び演算増幅回路39を用いて、差分信号の巡回型A/D変換のための処理を行う。サブA/D変換回路25は、演算増幅回路39の出力(例えば、非反転出力)39aからの信号VOPを受ける。
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Patent Agency Ranking
公开(公告)号：JP4654998B2
公开(公告)日：2011-03-23
申请号：JP2006203205
申请日：2006-07-26
Applicant: 株式会社デンソー
Inventor： 哲哉 牧原
CPC classification number: G11C27/026 , H03M1/0607 , H03M1/0682 , H03M1/0695 , H03M1/162 , H03M1/164
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公开(公告)号：JPWO2009034683A1
公开(公告)日：2010-12-24
申请号：JP2009532049
申请日：2008-08-21
Applicant: パナソニック株式会社
IPC: H03M1/44
CPC classification number: H03M1/0678 , H03M1/0695 , H03M1/44
Abstract: パイプライン型AD変換器(1)は、複数の変換ステージ(11,11,…)を備える。変換ステージの各々において、アナログ・デジタル変換回路(101)は、前段からの入力電圧(Vin)をデジタルコード(Dout)に変換する。デジタル・アナログ変換回路(102)は、アナログ・デジタル変換回路によって得られたデジタルコードを中間電圧(Vda)に変換する。電荷演算回路(103)は、入力電圧をサンプリングする容量部(C1,C2)と、容量部によってサンプリングされた入力電圧と前記デジタル・アナログ変換回路によって得られた中間電圧との混合電圧を増幅する増幅部(104)とを有する。増幅部(104)は、互いに同一の構成を有するとともに互いに並列接続された複数のオペアンプ(amp1,amp1,…)を含む。
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公开(公告)号：JP2010278985A
公开(公告)日：2010-12-09
申请号：JP2009132360
申请日：2009-06-01
Applicant: Texas Instr Japan Ltd , 日本テキサス・インスツルメンツ株式会社
Inventor： OYAMA SOICHIRO , ARIYOSHI KATSUHIKO
IPC: H03M1/14
CPC classification number: H03M1/002 , H03M1/0695 , H03M1/168
Abstract: PROBLEM TO BE SOLVED: To provide an analog/digital (A/D) conversion circuit allowing reduction of power consumption in accordance with an operation mode. SOLUTION: In the A/D conversion circuit, a conversion stage 20-1 is stopped under a power saving mode and an input signal to the conversion stage 20-1 is input to a subsequent conversion stage 20-2. Thus, A/D conversion is performed while reducing the number of conversion stages in comparison with a normal mode, thereby effectively reducing power consumption. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：提供一种模拟/数字（A / D）转换电路，其允许根据操作模式降低功耗。 解决方案：在A / D转换电路中，在省电模式下停止转换级20-1，并将转换级20-1的输入信号输入到后续的转换级20-2。 因此，与正常模式相比，在减少转换级数的同时进行A / D转换，从而有效地降低功耗。 版权所有（C）2011，JPO＆INPIT
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9.发明专利Reference voltage generation circuit, a/d converter and d/a converter 审中-公开参考电压发生电路，A / D转换器和D / A转换器
公开(公告)号：JP2010268387A
公开(公告)日：2010-11-25
申请号：JP2009120135
申请日：2009-05-18
Applicant: Panasonic Corp , パナソニック株式会社
Inventor： KITO TAKAYASU
CPC classification number: H03M1/002 , H03M1/0695 , H03M1/365 , H03M1/44 , H03M1/765
Abstract: PROBLEM TO BE SOLVED: To provide an A/D converter and a D/A converter including a reference voltage generation circuit by which the time for shifting to a power saving mode and the time for recovery therefrom are shortened and short-time intermittent operation is enabled.
SOLUTION: The reference voltage generation circuit includes: a reference voltage generation part 12 that is connected between a first reference voltage terminal VRT and a second reference voltage terminal VRB and that generates a plurality of reference voltages; capacitors 13a, 13b that are connected to the first and second reference voltage terminals, respectively; a reference voltage detection circuit 16 that detects voltage values at the first and second reference voltage terminals; current control circuits 11a, 11b that control a magnitude of a power supply current that is allowed to flow through the reference voltage generation part, in accordance with the voltage values detected by the reference voltage detection circuit; and switching means 14a to 14d that switch so as to replace the reference voltage generation part with a high-resistance element 15 during a power-saving mode. During the power-saving mode, by switching to the high-resistance element, a current flowing between the first and second reference voltage terminals is reduced, and the potentials of the capacitors are kept due to a minute current. Therefore, a recovery time from the power-saving mode becomes short.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 解决的问题：提供一种A / D转换器和D / A转换器，其包括用于转换到省电模式的时间和从其恢复的时间被缩短和短时间的参考电压产生电路 启用间歇操作。 参考电压产生电路包括：参考电压产生部分12，其连接在第一参考电压端子VRT和第二参考电压端子VRB之间，并产生多个参考电压; 电容器13a，13b分别连接到第一和第二参考电压端子; 检测第一和第二参考电压端子处的电压值的参考电压检测电路16; 电流控制电路11a，11b，其根据由基准电压检测电路检测的电压值来控制允许流过基准电压产生部的电源电流的大小; 以及切换装置14a至14d，其在省电模式期间切换以便用高电阻元件15替换基准电压产生部分。 在省电模式期间，通过切换到高电阻元件，在第一和第二参考电压端子之间流动的电流减小，并且电容器的电位由于微小电流而被保持。 因此，从省电模式的恢复时间变短。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP4583694B2
公开(公告)日：2010-11-17
申请号：JP2001560540
申请日：2000-08-25
Inventor： チアン，メーイ−リン
CPC classification number: H03M1/0695 , H03M1/0624 , H03M1/442
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