Wireless device and data reproduction method
    1.
    发明专利
    Wireless device and data reproduction method 审中-公开
    无线设备和数据复制方法

    公开(公告)号:JP2014086739A

    公开(公告)日:2014-05-12

    申请号:JP2012231287

    申请日:2012-10-19

    发明人: CHIBA WAKANA

    IPC分类号: H04L7/08

    摘要: PROBLEM TO BE SOLVED: To accurately reproduce first half data before synchronization detection without data reproduction time being redundant.SOLUTION: A wireless device includes: a storage unit which sequentially stores prescribed time length of detection data obtained by a reception unit; a synchronization detection unit which detects a synchronous word from the detection data stored in the storage unit; a symbol timing detection unit which determines the symbol timing of the detection data stored in the storage unit from the synchronous word; a DC offset detection unit which detects a DC offset of the detection data stored in the storage unit; and a data reproduction unit which extracts detection data for every symbol timing from the detection data of the first half data stored in the storage unit at the time when the synchronous word is detected by the synchronization detection unit and extracts a symbol value from the detection data for every symbol timing by cancelling the DC offset.

    摘要翻译: 要解决的问题:在同步检测之前准确地再现前半数据,而不需要冗余的数据再现时间。解决方案:一种无线设备包括:存储单元,其顺序地存储由接收单元获得的检测数据的规定时间长度; 同步检测单元,从存储在存储单元中的检测数据中检测同步字; 符号定时检测单元,其从同步字确定存储在存储单元中的检测数据的符号定时; DC偏移检测单元,其检测存储在存储单元中的检测数据的DC偏移; 以及数据再现单元,其从同步检测单元检测到同步字时的存储单元中存储的第一半数据的检测数据中提取每个符号定时的检测数据,并从检测数据中提取符号值 通过取消DC偏移量对每个符号定时。

    Slice circuit
    7.
    发明专利
    Slice circuit 审中-公开
    SLICE电路

    公开(公告)号:JP2004064196A

    公开(公告)日:2004-02-26

    申请号:JP2002216384

    申请日:2002-07-25

    摘要: PROBLEM TO BE SOLVED: To provide a slice circuit capable of accurately converting an input analog signal into a digital signal even when the input signal includes a drift of fast changing DC offset. SOLUTION: The slice circuit 90 includes: a DC component adjustment circuit 92; an integrator 93; an LPF 94; and a comparator 95. The DC component adjustment circuit 92 adjusts only a DC component of the input signal received from an input terminal 91 so that the result has a DC component comprising a prescribed voltage level. The integrator 93 amplifies only high frequency components of a prescribed frequency or over in the input signal received from the DC component adjustment circuit 92. The LPF 94 detects an average voltage of the input signal received from the DC component adjustment circuit 92. The comparator 95 compares voltage of an output signal from the integrator 93 with voltage of an output signal from the LPF 94 and outputs a digital signal with a logic level depending on the result of comparison to an output terminal 96. COPYRIGHT: (C)2004,JPO

    摘要翻译: 要解决的问题:即使当输入信号包括快速变化的DC偏移的漂移时,提供能够将输入的模拟信号精确地转换成数字信号的片电路。 解决方案:片电路90包括:直流分量调节电路92; 积分器93; 一个LPF 94; 和比较器95.直流分量调整电路92仅调整从输入端子91接收的输入信号的直流分量,使得结果具有包括规定电压电平的直流分量。 积分器93仅放大从DC分量调整电路92接收的输入信号中的规定频率以上的高频成分。LPF 94检测从直流分量调整电路92接收的输入信号的平均电压。比较器95 将来自积分器93的输出信号的电压与来自LPF94的输出信号的电压进行比较,并根据与输出端子96的比较结果输出具有逻辑电平的数字信号。(C)2004 ,JPO

    無線受信機およびその周波数補正方法
    9.
    发明专利
    無線受信機およびその周波数補正方法 有权
    无线电接收机及其频率校正方法

    公开(公告)号:JP2015142287A

    公开(公告)日:2015-08-03

    申请号:JP2014014780

    申请日:2014-01-29

    发明人: 柴田 和則

    摘要: 【課題】FSKやQPSKなどの送受信周波数のずれが復調信号にDCオフセットとして現れる変調方式の無線受信機において、受信信号が帯域制限用フィルタでカットされることによる感度劣化を抑えつつ、ノイズ耐性を高める。 【解決手段】送受信の周波数偏差から求めた補正値Adj DCを復調(検波)信号から減算してオフセット補正を行う高速引き込み処理部102と、前記復調(検波)信号の平均値から求めた補正値Adj local(t)を局部発振器1012にフィードバックする低速引き込み処理部104とを併用し、高速引き込み処理の補正値Adj DCから補正量Adj Del(t)を減算することで、該補正値Adj DCを時間経過に伴い減少させつつ、前記フィードバックによって、高速引き込み処理の補正値Adj DCを低速引き込み処理に引き渡す。 【選択図】図14

    摘要翻译: 要解决的问题:在调制系统的无线电接收机中抑制由频带限制滤波器切断接收信号导致的灵敏度劣化的同时改善噪声,其中FSK或QPSK的发送和接收频率的偏差出现在解调信号中作为DC 偏移。解决方案:通过使用高速引入处理部102来进行偏移校正,通过从解调(检测)信号和低速拉出处理部件102中减去从发送和接收频率的偏差计算出的校正值Adj DC, 在处理部分104中,将从解调(检测)信号的平均值计算的校正值Adj local(t)馈送到本地振荡器1012,从校正值Adj Del(t)中减去校正值Adj Del(t) 高速拉入处理。 因此,在经过了时间的同时减小校正值Adj DC的同时,通过反馈将高速引入处理的校正值Adj DC传递到低速拉入处理。

    Fsk receiver
    10.
    发明专利

    公开(公告)号:JP5304089B2

    公开(公告)日:2013-10-02

    申请号:JP2008198883

    申请日:2008-07-31

    发明人: 和則 柴田

    IPC分类号: H04L27/14 H04B1/10 H04B1/16

    CPC分类号: H04L27/142

    摘要: In an FSK receiver according to the present invention, a correction operation for a DC offset component is performed based on a maximum value and a minimum value of a demodulation signal. If a difference between the maximum and minimum values is less than a predetermined threshold value TH1, the correction operation is halted. Thus, the FSK receiver can rapidly perform an appropriate offset removal from a multi-level FSK signal.