利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

1009 条记录 (耗时 0.015 秒)

    時計
    1.
    发明专利
    時計 审中-公开

    公开(公告)号：JP2020085600A

    公开(公告)日：2020-06-04

    申请号：JP2018218548

    申请日：2018-11-21

    申请人： セイコーインスツル株式会社

    发明人： 及川 亮太

    IPC分类号： G04C9/08 ,  G04G15/00 ,  G04G5/02

    摘要： 【課題】残り数量の計数の起点となる設定数量の調整に伴う煩わしさを軽減することができる時計を提供することを目的とする。 【解決手段】時計は、所定範囲の中の一つの数量を第1初期数量に設定する数量設定部と、所定範囲の上限又は下限までの残り数量の計数の起点となる設定数量の調整を開始させるよう指示する開始信号及び設定数量の調整を終了させるよう指示する終了信号を受信する信号受信部と、信号受信部が開始信号を受信した第1開始時点から終了信号を受信する第1終了時点までの間、第1初期数量から所定範囲の上限又は下限まで規定時間で到達するように所定範囲の上限又は下限に向かって設定数量を変化させる第1調整処理を実行する数量調整部と、第1初期数量又は設定数量を表示する数量表示部と、を備える。 【選択図】図1

    Electronic timepiece
    3.
    发明专利
    Electronic timepiece 有权
    电子计时器

    公开(公告)号：JP2008151567A

    公开(公告)日：2008-07-03

    申请号：JP2006338172

    申请日：2006-12-15

    申请人： Citizen Holdings Co Ltd ,  シチズンホールディングス株式会社

    发明人： NAKAYAMA YASUAKI

    IPC分类号： G04C9/08 ,  G04G5/02

    摘要： PROBLEM TO BE SOLVED: To provide an electronic timepiece of an electromagnetic correction system having excellent operability of time correction, and operable intelligibly and surely especially when correcting a time continuously. SOLUTION: This timepiece is equipped with a time reference source 2, a timepiece circuit 3, a display part 6 for displaying time information of the timepiece circuit 3, motors 5a, 5b for driving the display part 6, a winding crown 10 for correcting the time information of the timepiece circuit 3 by manual operation, and a correction control part 20 for correcting the time information continuously by transferring to a continuous display driving correction mode via a continuous display driving preparation period when a switching condition reaches a prescribed condition by operating the winding crown 10. The correction control part 20 has a constitution for driving the motors 5a, 5b in a prescribed period with a driving frequency which is different from a driving frequency in the continuous display driving correction mode, or with a prescribed number of motor driving signals P4, P5, during the continuous display driving preparation period. COPYRIGHT: (C)2008,JPO&INPIT

    摘要翻译： 要解决的问题：提供具有优异的时间校正可操作性的电磁校正系统的电子表，并且可以可靠地且可靠地进行操作，特别是在连续校正时间时。

    解决方案：该时计配备有时间基准源2，钟表电路3，显示时钟电路3的时间信息的显示部6，驱动显示部6的马达5a，5b，卷绕表冠10 用于通过手动操作来校正时计电路3的时间信息;以及校正控制部20，用于通过在切换条件达到规定条件时通过连续显示驱动准备期间转移到连续显示驱动校正模式来连续校正时间信息 修正控制部20具有在规定期间以与连续显示驱动校正模式中的驱动频率不同的驱动频率或规定数量驱动电动机5a，5b的结构 的电动机驱动信号P4，P5。 版权所有（C）2008，JPO＆INPIT

    Time changing method and clock circuit using the same
    4.
    发明专利
    Time changing method and clock circuit using the same 有权

    公开(公告)号：JP2004077417A

    公开(公告)日：2004-03-11

    申请号：JP2002241652

    申请日：2002-08-22

    申请人： Yokogawa Electric Corp ,  横河電機株式会社

    发明人： YOKOI TOYOAKI

    IPC分类号： G04G5/02 ,  G04G3/02

    摘要： PROBLEM TO BE SOLVED: To solve the problem wherein interrupt signals must maintain a constant period, and thus it takes much time to change time of a clock circuit for generating interrupt signals.
    SOLUTION: Only for a time longer than the period of interrupt signals, a count value generating time is changed to a time to be set, and for a time shorter than the period of interrupt signals, the period of millisecond pulse signals is changed and adjusted in a given period by a smooth adjusting circuit. The time changes are possible in a short time.
    COPYRIGHT: (C)2004,JPO

    ELECTRONIC APPARATUS HAVING CLOCK CIRCUIT
    5.
    发明专利
    ELECTRONIC APPARATUS HAVING CLOCK CIRCUIT 审中-公开

    公开(公告)号：JP2003240883A

    公开(公告)日：2003-08-27

    申请号：JP2002040987

    申请日：2002-02-19

    申请人： MURATA MACHINERY LTD

    发明人： NISHIOKA NAOKI

    IPC分类号： G04G5/02 ,  G04G5/00

    摘要： PROBLEM TO BE SOLVED: To provide an electronic apparatus having a clock circuit capable of fine-tuning time shift without complicating a circuit structure. SOLUTION: Time is counted by a timer (ST1 and ST2). A temperature T is measured (ST4) every time 30 min. elapses (ST3). A deviation Δf (T) of a frequency at the temperature T from a frequency f (20) at 20°C of an oscillator is extracted from a table used for storing it in advance (ST5). Low three digits (d) of the deviation Δf (T) of the frequency are accumulated (ST6). When the cumulative value D exceeds 7,200, a clock is delayed by one second (ST8), and 7,200 is subtracted from the cumulative value D (ST9). When the cumulative value falls below -7,200, the clock is advanced by one second (ST11), and 7,200 is added to the cumulative value D (ST12). COPYRIGHT: (C)2003,JPO

    CLOCK MECHANISM
    8.
    发明专利
    CLOCK MECHANISM 失效

    公开(公告)号：JPH07306277A

    公开(公告)日：1995-11-21

    申请号：JP9898694

    申请日：1994-05-13

    申请人： FUJITSU LTD

    发明人： SAKURAI MITSUO ,  HIRAI YOSHIRO ,  KITAMI TOSHIYUKI ,  YAMAMOTO MASAO ,  WADA MIKAYO

    IPC分类号： G04G5/02 ,  G04C9/08 ,  G06F1/14

    摘要： PURPOSE:To provide a clock mechanism being employed in an information processor in which the accuracy is enhanced by resetting the time freely while reflecting the reset time gradually. CONSTITUTION:The clock mechanism comprises a time counter 1 for counting the input clock to display the time, a time information input means 2, means 3 for calculating the time error based on the difference between input time information and the content of the time counter 1, and means 4 for distributing the time error generate a corrected time series sequentially being set in the time counter 1. A clock control means for increasing/decreasing the number of clock pulses being inputted to the time counter 1 for a designated period according to an error direction flag carrying the sign of error and the value thereof, may be substituted for the corrected time setting means 4.