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291 条记录 (耗时 0.024 秒)

    タイミングイベント検出
    1.
    发明专利
    タイミングイベント検出 审中-公开

    公开(公告)号：JP2020530217A

    公开(公告)日：2020-10-15

    申请号：JP2019570576

    申请日：2017-06-22

    申请人： ミニマ プロセッサー オイ

    发明人： パーシオ アリ ,  トゥルンクイスト マシュー ,  コスキネン ラウリ

    IPC分类号： H03K5/1534 ,  H03K19/096

    摘要： タイミングイベント検出を提供することを目的とする。第1の態様によれば、デバイスは、非検出期間の間、クロック条件バッファの出力を第1の状態にセットするように構成されたクロック条件バッファを備え、前記クロック条件バッファは、さらに、検出期間の間、前記出力を前記第1の状態から第2の状態へトグルするようにさらに構成され、前記クロック条件バッファは、前記出力が、前記検出期間の間の一方向にのみトグルすることを保証するようにさらに構成される。これは、偽のイベント検出を防止する。さらに、タイミングポイントに関して、パルス幅が低電圧で管理することが困難であり得る場合、パルス無しで動作可能である。 【選択図】図1

    Phase adjustment circuit and phase adjustment method
    5.
    发明专利
    Phase adjustment circuit and phase adjustment method 有权
    相位调整电路和相位调整方法

    公开(公告)号：JP2007215021A

    公开(公告)日：2007-08-23

    申请号：JP2006034150

    申请日：2006-02-10

    申请人： Fujitsu Ltd ,  富士通株式会社

    发明人： ITO SACHIKO ,  NISHIZONO KAZUNORI

    IPC分类号： H03K5/00 ,  H03K4/06 ,  H03K5/1532 ,  H03K5/1534

    CPC分类号： H03K5/1534

    摘要： PROBLEM TO BE SOLVED: To provide a phase adjustment circuit and a phase adjustment method by which variation of a phase shift amount is prevented even when frequency of carrier waves for transmitting a sensor signal is varied. SOLUTION: A triangular wave conversion circuit 2G converts a pulse train signal VPSIN into triangular waves VC. A triangular wave amplitude control circuit 3G compares an amplification value of the triangular waves VC with an amplitude reference value VPAJ and outputs an adjustment signal AS according to difference between both to the triangular wave conversion circuit 2G. The triangular wave conversion circuit 2G adjusts the amplitude value of the triangular waves VC by varying inclinations of the triangular waves VC according to the adjustment signal AS. Thus, a feedback loop is constituted and the amplification value of the triangular wave VC is maintained at a fixed value according to the amplitude reference value VPAJ. A phase shift circuit 4 outputs a phase-shift pulse train signal VPSOUT which is a pulse train signal whose phase is shifted to the original pulse train signal VPSIN. COPYRIGHT: (C)2007,JPO&INPIT

    摘要翻译： 要解决的问题：提供一种相位调整电路和相位调整方法，通过该相位调整电路和相位调整方法，即使改变用于传送传感器信号的载波的频率，也可以防止相移量的变化。 解决方案：三角波转换电路2G将脉冲串信号VPSIN转换为三角波VC。 三角波幅度控制电路3G将三角波VC的放大值与幅度基准值VPAJ进行比较，并根据三角波变换电路2G的差异输出调整信号AS。 三角波变换电路2G通过根据调整信号AS改变三角波VC的倾斜度来调整三角波VC的振幅值。 因此，构成反馈回路，根据振幅基准值VPAJ将三角波VC的放大值维持在固定值。 相移电路4输出相移到原始脉冲串信号VPSIN的脉冲序列信号的相移脉冲串信号VPSOUT。 版权所有（C）2007，JPO＆INPIT

    Sampling circuit, sampling method, program therefor, recording medium, and electronic apparatus
    8.
    发明专利
    Sampling circuit, sampling method, program therefor, recording medium, and electronic apparatus 审中-公开

    公开(公告)号：JP2004282259A

    公开(公告)日：2004-10-07

    申请号：JP2003068750

    申请日：2003-03-13

    申请人： Sharp Corp ,  シャープ株式会社

    发明人： IKEDA YUTAKA ,  ARAMAKI TAKASHI

    IPC分类号： H03K5/1532 ,  H03K5/1534 ,  H04N5/00

    摘要： PROBLEM TO BE SOLVED: To provide a sampling circuit capable of enhancing the accuracy of reproduction while suppressing increase in data amount in the case of wirelessly transmitting and reproducing a control signal, and to provide a sampling method, a program therefor, a recording medium, and an electronic apparatus. SOLUTION: The sampling circuit is provided with: a first sampling circuit 102 for sampling an input signal 101 with a first sampling clock 106 faster than a data speed of the input signal 101 to produce a first sampling signal 103; and a second sampling circuit 104 for sampling the first sampling signal 103 with a second sampling clock 109 faster than the data speed of the input signal 101 and slower than the first sampling signal 103 to produce a second sampling signal 105. COPYRIGHT: (C)2005,JPO&NCIPI

    RECEPTION DATA DETECTING CIRCUIT
    9.
    发明专利
    RECEPTION DATA DETECTING CIRCUIT 失效

    公开(公告)号：JP2002246991A

    公开(公告)日：2002-08-30

    申请号：JP2001043504

    申请日：2001-02-20

    申请人： TOA CORP

    发明人： EJIMA KENICHI

    IPC分类号： G06F11/00 ,  H03K5/1532 ,  H03K5/1534 ,  H04B17/00 ,  H04L1/00

    摘要： PROBLEM TO BE SOLVED: To enable detection of errors, using a general-use circuit. SOLUTION: A master clock generator 8 generates a clock signal, having a period shorter than a H or L level interval, if reception data are received normally. An edge detection circuit 4 generates an edge detection signal, each time, it detects an edge of the receive data. A counter 6 starts counting master clock signals, each time the edge detection signal is generated. An error detection circuit 10 compares the counted value of the counter 6 with a value corresponding to a length which is allowable as the H or L level interval, each time the edge detection signal is generated.

    CLOCK SIGNAL CORRECTING CIRCUIT AND SEMICONDUCTOR DEVICE
    10.
    发明专利
    CLOCK SIGNAL CORRECTING CIRCUIT AND SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2002217697A

    公开(公告)日：2002-08-02

    申请号：JP2001011174

    申请日：2001-01-19

    申请人： FUJITSU QUANTUM DEVICES LTD

    发明人： ONO MASAAKI ,  KAZUNO MASATAKA ,  MATSUNO SHIGETO

    IPC分类号： H03K5/13 ,  H03K5/1532 ,  H03K5/1534 ,  H03K5/156 ,  H03K5/159

    摘要： PROBLEM TO BE SOLVED: To correct the duty ratio of clock signals with accuracy by means of a simple circuit. SOLUTION: A frequency dividing means 20 generates a frequency-divided clock signal by dividing the frequency of an input clock signal into 1/n frequencies (n: a natural number). An edge detecting means 21 detects the edge of the frequency-divided clock signal. A delaying means 22 generates a delayed frequency-divided clock signal by delaying the frequency-divided clock signal in accordance with the detected results of the detecting means 21. An arithmetic means 23 generates an output clock signal by operating the frequency-divided clock signal and delayed frequency-divided clock signal.