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公开(公告)号：JPWO2020065694A1
公开(公告)日：2021-08-30
申请号：JP2018035248
申请日：2018-09-25
Applicant: サンケン電気株式会社
Inventor： 林 秀樹
Abstract: 高い解像度のAD変換と、複数のアナログ信号に対する低い解像度のAD変換との両方のニーズを満たすことができるアナログデジタル変換器を提供する。 VCCとGNDとの間に接続された直列抵抗回路(11)によって等しい電位の間隔を有する複数個のリファレンス電圧を生成し、入力されたアナログ信号とそれぞれ比較することでデジタル値に変換する単位回路(10 1 )、(10 2 )と、単位回路(10 1 )、(10 2 )でそれぞれ変換されたデジタル値を加算する加算器(20)とを具備し、単位回路(10 1 )、(10 2 )の直列抵抗回路(11)を連結させてVCCとGNDとの間に接続する連結スイッチ(第1スイッチSW1、第2スイッチSW2及び第4スイッチSW4)と、入力されたアナログ信号を単位回路(10 1 )、(10 2 )で共通化する共通化スイッチ(第3スイッチSW3)とを備えている。
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公开(公告)号：JP2016217937A
公开(公告)日：2016-12-22
申请号：JP2015104526
申请日：2015-05-22
Applicant: 日本セラミック株式会社
IPC: G01J1/02 , H03M1/20 , H03K17/945 , G01J1/42
Abstract: 【課題】ポップコーン性ノイズに対する耐量を上げた焦電型赤外線人体検知装置を提供する。 【解決手段】チタン酸ジルコン酸鉛などからなる焦電型光電変換素子から生じる焦電電流をIV変換器で電圧変換し電圧出力しアンプ回路で電圧増幅する事なくマイクロコンピュータなどの演算手段に直接入力する。 【選択図】図1
Abstract translation: 提供一种热电型红外线人体检测装置提高承受针对爆米花噪声。 甲直接到计算装置，例如没有电压放大的微型计算机从由放大器电路IV转换器中的电压转换和电压输出由锆钛酸铅的热电光电转换元件产生的热电电流 进入。 点域1
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公开(公告)号：JP5680796B2
公开(公告)日：2015-03-04
申请号：JP2014512132
申请日：2012-05-25
Applicant: アナログ ディヴァイスィズ インク , アナログ ディヴァイスィズ インク
Inventor： ロナルド・エー・カプスタ , ドリス・リン , ヤーヴァント・ダーメンジャン
IPC: H03M1/20
CPC classification number: H03M1/0641 , H03M1/12
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公开(公告)号：JP4763644B2
公开(公告)日：2011-08-31
申请号：JP2007091124
申请日：2007-03-30
Applicant: ルネサスエレクトロニクス株式会社
Inventor： 哲弘 小山
Abstract: According to one aspect of the present invention, there is provided a dither circuit including a dither generating circuit generating a plurality of complementary signal pairs, and a dither input circuit generating a plurality of dither signals from the plurality of complementary signal pairs to add the generated dither signals to an analog input signal, in which the plurality of complementary signal pairs have different frequencies with each other, the dither input circuit includes capacitors provided for each of the plurality of complementary signal pairs and a plurality of switch pairs including first and second switches having one terminals connected to each one terminal of the capacitors, and the other terminals of the capacitors are connected to an adding point to the analog input signal, the first switch supplies ones of the complementary signal pairs to one terminals of the capacitors when a clock signal is in effective state, and the second switch supplies the others of the complementary signal pairs to one terminals of the capacitors when an inverting clock signal of the clock signal is in effective state.
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5.发明专利
公开(公告)号：JP2011024190A
公开(公告)日：2011-02-03
申请号：JP2010108120
申请日：2010-05-10
Applicant: Honeywell Internatl Inc , ハネウェル・インターナショナル・インコーポレーテッド
Inventor： GRAETZ ERNEST FRANK JOHN , KUEBER KIRBY , TRINKLE WILLIAM JOSEPH
CPC classification number: H03M1/0641 , H03B29/00 , H03M1/12
Abstract: PROBLEM TO BE SOLVED: To provide systems and methods for improving resolution of low-noise signals in an analog-to-digital (A/D) conversion circuit.
SOLUTION: A simple, low cost pseudo-noise generating circuit is disclosed that, when connected to signal conditioning circuitry of an A/D conversion circuit, adds pseudo-noise to an analog input voltage signal. Additional pseudo-noise is beneficial for improving the resolution of A/D conversion when oversampling and summing or averaging are used in post-conversion processing operations. The circuit is composed of a plurality of resistors configured in at least two parallel branches. An individually switchable voltage source output is connected to each branch. A resulting analog voltage is measured at a common termination point for the branches, depending on the combination of switchable voltage source outputs turned on, and the branch to which the voltage output is applied. By varying the combination of switchable voltage source outputs turned on over time, a known analog pseudo-noise signal is developed.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：提供用于提高模数（A / D）转换电路中低噪声信号分辨率的系统和方法。 解决方案：公开了一种简单的低成本伪噪声产生电路，当连接到A / D转换电路的信号调节电路时，将伪噪声添加到模拟输入电压信号。 当在后转换处理操作中使用过采样和求和或平均时，额外的伪噪声有利于提高A / D转换的分辨率。 电路由配置在至少两个平行分支中的多个电阻器组成。 单独可切换的电压源输出连接到每个分支。 根据开关的可切换电压源输出的组合和施加电压输出的分支，在分支的公共终端点测量结果模拟电压。 通过改变随时间导通的可切换电压源输出的组合，开发了已知的模拟伪噪声信号。 版权所有（C）2011，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：JP2008236755A
公开(公告)日：2008-10-02
申请号：JP2008073401
申请日：2008-03-21
Applicant: Honeywell Internatl Inc , ハネウェル・インターナショナル・インコーポレーテッド
Inventor： NEWLIN MATTHEW P , STANDJORD LEE K , GREENING THOMAS C , KEITH GREGORY W
CPC classification number: H03M1/0641 , G06F7/588 , H03M1/201 , H03M1/661
Abstract: PROBLEM TO BE SOLVED: To provide systems and methods for improving efficiency of a data converter.
SOLUTION: An example method generates a noise signal, alters the spectrum of the noise signal based on operation of an associated data converter, and supplies the altered spectrum noise signal to the associated data converter. The data converter is a digital-to-analog converter or an analog-to-digital converter. The altered spectrum noise signal is notched at frequencies of interest. The spectrum is altered by sending a signal generated by a random number generator to a delay device and adding the output of the delay device from the output of the random number generator. Also, the spectrum is altered by seeding first and second identical random number generators, delaying the operation of the first random number generator, and adding the output of the delayed first random number generator from the second random number generator.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：提供用于提高数据转换器效率的系统和方法。 解决方案：示例性方法产生噪声信号，基于相关联的数据转换器的操作改变噪声信号的频谱，并将改变的频谱噪声信号提供给相关联的数据转换器。 数据转换器是数模转换器或模数转换器。 改变的频谱噪声信号在感兴趣的频率处被切断。 通过将随机数发生器产生的信号发送到延迟装置并且从随机数发生器的输出添加延迟装置的输出来改变频谱。 此外，通过播种第一和第二相同的随机数发生器来改变频谱，延迟第一随机数发生器的操作，以及将来自第二随机数发生器的延迟的第一随机数发生器的输出相加。 版权所有（C）2009，JPO＆INPIT
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公开(公告)号：JP2007243620A
公开(公告)日：2007-09-20
申请号：JP2006063353
申请日：2006-03-08
Applicant: Toyota Motor Corp , トヨタ自動車株式会社
Inventor： WATANABE HIKARI
Abstract: PROBLEM TO BE SOLVED: To make a ΔΣ AD modulator low-order to attain a low cost of a ΔΣ type AD converter and obtain a higher-precision AD converter with a small-scale analogue circuit, and besides decrease a chip area of the whole of the ΔΣ AD modulator to make circuit design easy.
SOLUTION: There is provided the ΔΣ type AD converter which is equipped with the ΔΣ AD modulator 10, a multi-bit counter 20 which counts an output of the ΔΣ AD modulator 10, and a deformation filter 2 which performs the filter processing of an output of the multi-bit counter 20. The multi-bit counter 20 counts 1-bit data outputted from the ΔΣ AD modulator 10 at each given period to output the data as multi-bit data.
COPYRIGHT: (C)2007,JPO&INPITAbstract translation: 要解决的问题：为了使ΔΣAD调制器低阶，以获得ΔΣ型AD转换器的低成本，并且获得具有小规模模拟电路的更高精度的AD转换器，并且除了减小芯片面积 的整个ΔΣAD调制器，使电路设计容易。 解决方案：提供了配备有ΔΣAD调制器10的ΔΣ型AD转换器，对ΔΣAD调制器10的输出进行计数的多位计数器20和执行滤波处理的变形滤波器2 多位计数器20对每个给定周期从ΔΣAD调制器10输出的1位数据进行计数，以将数据输出为多位数据。 版权所有（C）2007，JPO＆INPIT
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公开(公告)号：JP2005295556A
公开(公告)日：2005-10-20
申请号：JP2005099842
申请日：2005-03-30
Applicant: Tektronix Inc , テクトロニクス・インコーポレイテッドTektronix,Inc.
Inventor： SLAVIN KEITH R
CPC classification number: H03M1/0639 , H03M1/12
Abstract: PROBLEM TO BE SOLVED: To provide a dither circuit capable of more efficiently reducing quantization noise in a quantizing device, particularly in a multi-stage analog-to-digital converter (ADC) 16.
SOLUTION: A divide-by-3 circuit 12 generates a signal having a frequency of [sampling frequency]/3, from a sampling clock for ADC, and this signal is processed by a re-timing register 18 and a filter 14 to generate a dither signal. An adder 20 combines an analog signal to be digitized with the dither signal and supplies a resultant signal to the ADC 16. A cancellation signal is generated from a digital format signal of the dither signal by blocks 22, 24, 26, 28, 30, an adder circuit 32 combines the cancellation signal with a digital output signal of the ADC, and a corrected digital output signal having reduced quantization distortion is generated.
COPYRIGHT: (C)2006,JPO&NCIPIAbstract translation: 要解决的问题：提供能够更有效地降低量化装置中的量化噪声的抖动电路，特别是在多级模数转换器（ADC）16中。解决方案： 旁路3电路12从ADC的采样时钟产生具有[采样频率] / 3的频率的信号，并且该信号由重新定时寄存器18和滤波器14处理以产生抖动信号。 加法器20将要被数字化的模拟信号与抖动信号组合，并将结果信号提供给ADC 16.根据抖动信号的数字格式信号，通过块22,24,26,28,30， 加法器电路32将消除信号与ADC的数字输出信号组合，并且产生具有减小的量化失真的校正数字输出信号。 版权所有（C）2006，JPO＆NCIPI
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