公开(公告)号：KR1020050085013A

公开(公告)日：2005-08-29

申请号：KR1020057008826

申请日：2003-10-14

Applicant: 소니 모빌 커뮤니케이션즈 에이비

Inventor： 홈베르그페르

IPC: H05K7/00 ,  H05K7/12

CPC classification number: H05K9/0026 ,  H05K1/0218 ,  H05K3/301 ,  H05K2201/0133 ,  H05K2201/10371 ,  H05K2201/10393 ,  H05K2201/2045

Abstract: A method of providing support for an electronic component (17) in an electronic device comprising a PCB (printed circuit board) (14) and a structural element (15) covering at least a part of the PCB (14). The method comprises the steps of mounting the electronic component (17) on the PCB (14), applying an elastically compressible and shock-absorbing material (18) to the structural element (15) at an area (22) thereof that is adapted to cover the component (17), and assembling the PCB (14) and the structural element (15) in such manner that the elastically compressible and shock-absorbing material (18) exerts a pressure on the electronic component (17) towards the PCB (14). An electronic device comprising an elastically compressible and shock- absorbing material between the structural element and the PCB is also disclosed.

Abstract translation: 一种在包括PCB（印刷电路板））和覆盖PCB（14）的至少一部分的结构元件（15）的电子设备中为电子部件（17）提供支撑的方法。 该方法包括以下步骤：将电子部件（17）安装在PCB（14）上，在其区域（22）处将可弹性压缩和减震材料（18）施加到结构元件（15），该区域适于 覆盖部件（17），以及组装PCB（14）和结构元件（15），使得弹性可压缩和减震材料（18）朝着PCB向电子部件（17）施加压力 14）。 还公开了一种在结构元件和PCB之间包括可弹性压缩和减震材料的电子设备。

公开(公告)号：KR1020050066383A

公开(公告)日：2005-06-30

申请号：KR1020030097664

申请日：2003-12-26

Applicant: 엘지전자 주식회사

Inventor： 이창주 ,  박재수

IPC: H01R13/648

CPC classification number: H05K1/0218 ,  H01R12/57 ,  H01R13/648

Abstract: 본 발명은 인쇄회로기판의 커넥터 그라운드구조에 관한 것이다. 본 발명은 다수의 부품이 실장되고 외부와의 전기적 연결을 위한 케이블(61)이 커넥터(41)에 연결되는 인쇄회로기판에 있어서, 상기 부품이 실장되는 영역의 메인그라운드영역(47)이 상기 커넥터(41)가 실장되는 부분의 커넥터그라운드영역(42)과 분리되어 형성되고, 상기 부품이 실장되는 곳의 그라운드영역(47)과 상기 커넥터(41)가 실장되는 곳의 그라운드영역(42)이 비드(49)를 통해 연결된다. 상기 커넥터(41)가 실장되는 부품실장층(40)과 다른 층인 그라운드층(50)에도 상기 부품이 실장되는 곳의 그라운드영역(57)과 상기 커넥터(41)가 실장되는 곳의 그라운드영역(52)이 분리되어 형성되고, 상기 커넥터(41)가 실장되는 곳의 그라운드영역(42)과 다른 층에 구비되는 그라운드영역(52)은 비어홀(43)을 통해 상기 커넥터(41)가 실장되는 곳에 구비되는 그라운드영역(42)과 서로 전기적으로 연결된다.

公开(公告)号：KR100489860B1

公开(公告)日：2005-05-17

申请号：KR1019997003646

申请日：1997-10-23

Applicant: 텔레폰악티에볼라겟엘엠에릭슨(펍)

Inventor： 랄손안더스

IPC: H05K9/00

CPC classification number: H05K9/0024 ,  H05K1/0218 ,  Y10T29/49144 ,  Y10T29/49146

Abstract: 본 발명은 회로 기판(1)상의 전자 부품들을 차폐하는 장치 및 방법에 관한 것이다. 내부 표면(7) 및 외부 표면(6)을 포함하는 차폐 유닛(3)은 예컨대, 땜납에 의해 회로 기판(1)상에 고정되고, 차폐 유닛(3)은 다수의 전자 부품들을 둘러싼다. 차폐 유닛의 내부 표면(7)과 외부 표면(6)에 가장 근접하게 위치되는 전자 부품들은, 회로 기판(1)상의 공통 접지 접속부에 결합되는 폴(P1, P2, P3, P4)을 포함한다. 이 전자 부품들은 폴(P1, P2, P3, P4)이 차폐 유닛의 내부 표면(7) 및 외부 표면(6)을 향해 각각 면하도록 회로 기판(1)상에 배열된다. 이 전자 부품들은 또한, 상기 내부 표면(7) 및 상기 외부 표면(6)을 향해 각각 면하는 이 전자 부품들의 면이 회로 기판(1)상의 다른 전자 부품들(K1, K2, K3, K4)로부터 적어도 일정한 거리(d)에 위치되도록 회로 기판(1)상에 배열된다. 여러 가지 변형예들이 이 출원서에 설명된다.

公开(公告)号：KR1020050032300A

公开(公告)日：2005-04-07

申请号：KR1020030068333

申请日：2003-10-01

Applicant: 한화테크윈 주식회사

Inventor： 조세훈

IPC: G06K19/077

CPC classification number: G06K19/07779 ,  G06K19/07749 ,  G06K19/07783 ,  H05K1/0218 ,  H05K1/095 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/09036 ,  H05K2203/0108 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate of circuit board is provided to simplify a manufacturing process and enable the mass production. In a smart label, the first terminal(402) and the second terminal(406) constitute a closed circuit with a chip(414). A connection pattern is formed in a lower substrate of the circuit in oder to connect the first terminal(402) and the second terminal(406) of an antenna. The first terminal(402) and the second terminal(406) are electrically connected to a lower connection pattern by inserting a conductive paste through a paste inserting aperture(408).

Abstract translation: 提供电路基板的制造方法，以简化制造工序，实现批量生产。 在智能标签中，第一端子（402）和第二端子（406）构成具有芯片（414）的闭合电路。 在电路的下基板中形成连接图案以连接天线的第一端子（402）和第二端子（406）。 第一端子（402）和第二端子（406）通过插入导电浆料通过糊料插入孔（408）而电连接到下部连接图案。

公开(公告)号：KR1020050025749A

公开(公告)日：2005-03-14

申请号：KR1020030062570

申请日：2003-09-08

Applicant: 주식회사 팬택자산관리

Inventor： 이준희

IPC: H04B1/38

CPC classification number: H05K1/0218 ,  H05K1/0259 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09336 ,  H05K2201/10136

Abstract: A PCB structure related to an LCD signal line in a mobile terminal is provided to enhance the reliability and quality of a mobile terminal by performing a stable operation against an external abrupt situation, effectively use a PCB region, and reduce a unit cost by reducing an ESD(Electrostatic Discharge) protecting device in size. A PCB inner layer(22) is formed such that an LCD signal line is positioned at one region and a side region of the LCD signal line is allocated as a ground plane. A PCB upper layer(21) allows an upper portion of the PCB inner layer(22) to be allocated as the ground plane. A PCB lower layer(23) allows a lower portion of the PCB inner layer(22) to be allocated as the ground plane.

Abstract translation: 提供与移动终端中的LCD信号线相关的PCB结构，以通过对外部突发情况执行稳定操作来提高移动终端的可靠性和质量，有效地使用PCB区域，并通过减少单元成本来降低单元成本 ESD（静电放电）保护装置的尺寸。 PCB内层（22）形成为使得LCD信号线位于一个区域，并且LCD信号线的侧面区域被分配为接地层。 PCB上层（21）允许将PCB内层（22）的上部分配为接地层。 PCB下层（23）允许将PCB内层（22）的下部分配为接地层。

公开(公告)号：KR1020040090899A

公开(公告)日：2004-10-27

申请号：KR1020040026103

申请日：2004-04-16

Applicant: 알프스 덴키 가부시키가이샤

Inventor： 사이토요시오 ,  이토시게히로

IPC: H05K9/00

CPC classification number: H05K1/141 ,  H01R12/52 ,  H05K1/0218 ,  H05K3/3426 ,  H05K3/445 ,  H05K2201/10189 ,  H05K2201/10757 ,  H05K2201/10946

Abstract: PURPOSE: An electronic circuit unit is provided to achieve improved soldering reliability and shield effect between the electronic circuit unit and a mother board. CONSTITUTION: An electronic circuit unit comprises a circuit board(1) having an upper surface on which electronic components are mounted so as to form a desired electric circuit and a lower surface having a plurality of first land portions(3) connected to the electric circuit; and a connector member(4) arranged in a lower portion of the circuit board. The connector member has an insulating resin portion(4a), a metallic shield plate(5) buried in the insulating resin portion, and a connector terminal(6) having a first terminal portion(6a) exposed and protruded from an upper surface of the insulating resin portion and a second terminal(6c) exposed and protruded from a lower surface of the insulating resin portion. The first terminal portion protruded from the upper surface of the connector terminal is electrically connected to the first land portions and the second terminal portion protruded from the lower surface is electrically connected to second land portions(11) of a mother board(10).

Abstract translation: 目的：提供电子电路单元，以实现电子电路单元和母板之间的焊接可靠性和屏蔽效果的改善。 构成：电子电路单元包括电路板（1），电路板（1）具有安装有电子部件的上表面以形成所需的电路，下表面具有连接到电路的多个第一接地部（3） ; 以及布置在电路板的下部的连接器构件（4）。 连接器构件具有绝缘树脂部分（4a），埋在绝缘树脂部分中的金属屏蔽板（5）和连接器端子（6），其具有从第一端子部分（6a）的上表面露出并突出的第一端子部分 绝缘树脂部分和从绝缘树脂部分的下表面暴露和突出的第二端子（6c）。 从连接器端子的上表面突出的第一端子部分电连接到第一接地部分，并且从下表面突出的第二端子部分电连接到母板（10）的第二接地部分（11）。

公开(公告)号：KR1020040089558A

公开(公告)日：2004-10-21

申请号：KR1020040024802

申请日：2004-04-12

Applicant: 소니 주식회사

Inventor： 츠카모토소타로 ,  구로미야사토루 ,  하나이노부히로 ,  하야시다마사토

IPC: H05K1/18

CPC classification number: H01L23/552 ,  H01L23/49805 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/185 ,  H05K2201/09609 ,  H01L2224/05599

Abstract: PURPOSE: An interconnection board and a circuit module is provided to eliminate a shield gap by shielding integrated circuits with shielding interconnection films and shielding interlayer connection conductor films. CONSTITUTION: An interconnection board includes an interlayer dielectric(12), a multilayer interconnection film(10), an interlayer-connection conductor film, at least one bare semiconductor integrated circuit device(16), first and second shield interconnection film, and a plurality of shield interlayer-connection conductor films. The multilayer interconnection film is arranged at one or between two interlayer dielectrics. Each of the interlayer-connection conductor films forms an electrical connection between at least two of the interlayer dielectrics. The first shield interconnection film is provided above the semiconductor IC and the second shield interconnection film is provided below the semiconductor IC. The shield interlayer-connection conductor films are provided so as to surround the semiconductor IC and to provide electrical connections between the first shield and second shield interconnection films. Each shield interlayer-connection conductor film extends through at least one of the interlayer dielectric.

Abstract translation: 目的：提供互连板和电路模块，通过屏蔽集成电路屏蔽互连膜和屏蔽层间连接导体膜来消除屏蔽间隙。 构成：互连板包括层间电介质（12），多层互连膜（10），层间连接导体膜，至少一个裸半导体集成电路器件（16），第一和第二屏蔽互连膜以及多个 的屏蔽层间连接导体膜。 多层互连膜布置在两个层间电介质之间或之间。 每个层间连接导体膜在至少两个层间电介质之间形成电连接。 第一屏蔽互连膜设置在半导体IC上方，第二屏蔽互连膜设置在半导体IC的下方。 屏蔽层间连接导体膜设置成围绕半导体IC并且提供第一屏蔽和第二屏蔽互连膜之间的电连接。 每个屏蔽层间连接导体膜延伸穿过层间电介质中的至少一个。

公开(公告)号：KR1020040077511A

公开(公告)日：2004-09-04

申请号：KR1020040013125

申请日：2004-02-26

Applicant: 후루카와 덴키 고교 가부시키가이샤

Inventor： 요시하라야수히사 ,  키미지마히사오

IPC: H05K9/00

CPC classification number: C25D5/10 ,  C25D3/562 ,  C25D3/58 ,  C25D5/16 ,  H05K1/0218 ,  H05K3/384 ,  Y10T428/12063 ,  Y10T428/1209 ,  Y10T428/12438 ,  Y10T428/12569 ,  Y10T428/12681 ,  Y10T428/1291 ,  Y10T428/12993

Abstract: PURPOSE: A copper foil, a manufacturing method thereof, and an electromagnetic wave shielding body are provided to achieve improved shielding ability and transmittance, and prevent stain spots on the surface of the copper foil. CONSTITUTION: A copper foil comprises a fine roughening particle layer formed at least on one surface of the copper foil or a copper alloy foil; and a smoothing layer formed on the fine roughening particle layer and made of cobalt, nickel, indium, or an alloy thereof. The fine roughening particle is an alloy of copper, copper-cobalt, cobalt-nickel, or copper-cobalt-nickel. A stain-proof treatment is performed on the fine roughening particle layer. A silane coupling agent treatment is performed on the fine roughening particle layer.

Abstract translation: 目的：提供一种铜箔及其制造方法和电磁波屏蔽体，以提高屏蔽能力和透光率，并防止铜箔表面的污点。 构成：铜箔包括在铜箔或铜合金箔的至少一个表面上形成的细小的粗糙化颗粒层; 以及形成在细微粗糙化颗粒层上并由钴，镍，铟或其合金制成的平滑层。 细粗粒子是铜，铜 - 钴，钴 - 镍或铜 - 钴 - 镍的合金。 对细小粗糙化颗粒层进行防污处理。 在微细粗糙化颗粒层上进行硅烷偶联剂处理。

公开(公告)号：KR1020020055805A

公开(公告)日：2002-07-10

申请号：KR1020000085030

申请日：2000-12-29

Applicant: 삼성전기주식회사

Inventor： 류찬혁

IPC: H04B1/00

CPC classification number: H05K1/0218 ,  H04M1/0277 ,  H05K1/0231 ,  H05K3/249

Abstract: PURPOSE: A remote circuit board for a radio communication device is provided to form plenty of pads and signal lines by forming a silk layer on a dielectric layer, rather than a multi-type circuit board, easily obtain a ground layer, reduce a unit cost and make a product slim. CONSTITUTION: A pad(110) and a signal line(120) are formed at an upper surface and a lower surface of a dielectric layer(100). A silk layer(200) is formed at an entire upper surface of the dielectric layer(100), on which a pad(210) and a signal line(220) are formed. The pad(210) and the signal line(220) formed on the silk layer(200) are formed of carbon to reinforce their rigidity. The pad(110) and the signal line(120) on the dielectric layer(100) may be formed of carbon. Since the pad(210) and the signal line(220) are separately formed with the silk layer(200), a degree of freedom in designing can be obtained at the maximum, and especially, an area for forming a ground layer can be sufficiently obtained.

Abstract translation: 目的：提供无线电通信设备的远程电路板，通过在电介质层上形成丝网层而不是多类型电路板形成大量的焊盘和信号线，容易获得接地层，降低单位成本 并使产品变得苗条。 构成：在电介质层（100）的上表面和下表面处形成焊盘（110）和信号线（120）。 在电介质层（100）的整个上表面上形成有丝线层（200），在其上形成有焊盘（210）和信号线（220）。 形成在丝层（200）上的垫（210）和信号线（220）由碳形成以增强其刚性。 电介质层（100）上的焊盘（110）和信号线（120）可以由碳形成。 由于焊盘（210）和信号线（220）与丝网层（200）分开形成，所以可以最大限度地获得设计的自由度，特别是可以充分地形成接地层的区域 获得。

公开(公告)号：KR1020010076188A

公开(公告)日：2001-08-11

申请号：KR1020000051925

申请日：2000-09-04

Applicant: 미쓰비시덴키 가부시키가이샤

Inventor： 마쓰시마히로노리

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H05K1/0218 ,  H05K1/112 ,  H05K3/4602 ,  H01L2924/00

Abstract: PURPOSE: To provide a semiconductor device, with which the number of constitutive layers required for a multilayered substrate is reduced while keeping the location of solder bumps for signal to be connected to the electrodes of a semiconductor chip as conventional. CONSTITUTION: Since a signal line 12 of a first signal layer 9 is guided to a lower multilayered part via a through hole 15 selected on fixed conditions, even when a second signal layer 9 and the first signal layer 9 are overlapped without interposing a plane layer, a crosstalk noise does not become a problem. Besides, since a ground plane 14 is provided at the spot, where the signal line 12 is absent, of the first signal layer 9, even without providing the other plane layer between the first signal line 12 and the second signal layer 12, the second signal layer 12 can be made into strip structure held between planes. Thus, since one plane layer is unnecessitated, as a result, the number of layers required for the multilayered substrate can be reduced.

Abstract translation: 目的：提供一种半导体器件，其中减少了多层衬底所需的组成层数，同时保持了与常规连接到半导体芯片的电极的信号的焊料凸块的位置。 构成：由于第一信号层9的信号线12经由在固定条件下选择的通孔15被引导到下层多层部分，所以即使第二信号层9和第一信号层9重叠而不插入平面层 串扰噪声不成问题。 此外，由于在第一信号层9的不存在信号线12的点处设置接地层14，即使不在第一信号线12和第二信号层12之间提供另一平面层，第二信号层 信号层12可以制成保持在平面之间的带状结构。 因此，由于不需要一个平面层，结果可以减少多层基板所需的层数。