公开(公告)号：KR101020735B1

公开(公告)日：2011-03-09

申请号：KR1020080063160

申请日：2008-06-30

申请人： 주식회사 심텍홀딩스

发明人： 이종태 ,  오춘환 ,  정창보 ,  김태균 ,  차상석 ,  전현신

IPC分类号： H05K1/16 ,  H01G4/33

摘要： 박막 형태(Thin Film Type)의 유전체를 형성하고, 유전체의 상면에 접속될 상부전극을 임베디드 패턴(Embedded Pattern) 형태로 포함하는 제 1 인쇄회로기판을 형성하고, 유전체의 하면에 접속될 하부전극을 임베디드 패턴(Embedded Pattern) 형태로 포함하는 제 2 인쇄회로기판 형성하고, 유전체를 제 1 인쇄회로기판 및 제2인쇄회로기판 사이에 삽입하고, 제 1 인쇄회로기판 및 제2인쇄회로기판을 유전체가 사이에 삽입된 상태로 압착하고, 상부전극, 유전체 및 하부전극에 의해 형성되는 임베디드 캐패시터와 연결되고, 외부에 실장되는 집적회로 칩을 연결시키는 외부회로를 제1 및 제2인쇄회로기판 상에 형성하여, 인쇄회로기판의 두께를 감소시키면서도 높은 캐패시턴스를 구현 할 수 있는 임베디드 캐패시터를 포함하는 인쇄회로 기판 제조 방법을 제시한다.

公开(公告)号：KR1020100012712A

公开(公告)日：2010-02-08

申请号：KR1020080074257

申请日：2008-07-29

申请人： 주식회사 심텍홀딩스

发明人： 이종태 ,  오춘환 ,  정창보 ,  김태균 ,  차상석 ,  전현신

IPC分类号： H01K1/02 ,  H01L23/12

CPC分类号： H01L2224/16225 ,  H01L2924/1531

摘要： PURPOSE: A memory module printed circuit board for mounting a flip chip and a manufacturing method thereof are provided to reduce manufacturing time and costs by directly mounting the flip chip on a printed circuit board. CONSTITUTION: A printed circuit board(230) includes a buildup layer and a core with an internal circuit. A B2it(Buried Bump Interconnection Technology) bump(250) is formed on the surface of the PCB. The B2it bump connects the internal circuit, a flip chip bump pad(260), and an external circuit(265). The outermost layer is formed on the upper side of the printed circuit board and includes the external circuit and the flip chip bump pad for connecting the internal circuit to the flip chip with a DCA(Direct Chip Attach) method. The core and buildup layer includes a PTH(Plating Through Holes) or IVH(Interstitial Via Hole) structure(240).

摘要翻译： 目的：提供一种用于安装倒装芯片的存储模块印刷电路板及其制造方法，以通过将倒装芯片直接安装在印刷电路板上来减少制造时间和成本。 构成：印刷电路板（230）包括堆积层和具有内部电路的芯。 在PCB的表面上形成一个B2it（埋入式凸块互连技术）凸块（250）。 B2it凸块连接内部电路，倒装芯片凸块（260）和外部电路（265）。 最外层形成在印刷电路板的上侧，并且包括用DCA（直接芯片附接）方法将内部电路连接到倒装芯片的外部电路和倒装芯片凸块焊盘。 芯和堆积层包括PTH（电镀通孔）或IVH（间隙通孔）结构（240）。

公开(公告)号：KR1020100003060A

公开(公告)日：2010-01-07

申请号：KR1020080063160

申请日：2008-06-30

申请人： 주식회사 심텍홀딩스

发明人： 이종태 ,  오춘환 ,  정창보 ,  김태균 ,  차상석 ,  전현신

IPC分类号： H05K1/16 ,  H01G4/33

CPC分类号： H05K3/467 ,  H01G4/33 ,  H05K1/162 ,  H05K2201/0317 ,  H05K2203/0353

摘要： PURPOSE: A printed circuit board and a manufacturing method thereof are provided to obtain high capacitance by forming an upper electrode and a lower electrode with an embedded pattern type. CONSTITUTION: A dielectric is formed with a thin film type. The dielectric is formed by a sputtering, paste print or ink jet print method. The thickness of the dielectric is 10 um or less. A first printed circuit board(140) is arranged on the dielectric. The first printed circuit board includes an upper electrode(120) with an embedded pattern type. A second printed circuit board(150) is arranged under the dielectric. The second printed circuit board includes a lower electrode(130) with the embedded pattern type.

摘要翻译： 目的：提供印刷电路板及其制造方法，以通过形成具有嵌入图案类型的上电极和下电极来获得高电容。 构成：电介质由薄膜形成。 电介质通过溅射，糊状印刷或喷墨印刷法形成。 电介质的厚度为10μm以下。 第一印刷电路板（140）布置在电介质上。 第一印刷电路板包括具有嵌入图案类型的上电极（120）。 第二印刷电路板（150）布置在电介质下方。 第二印刷电路板包括具有嵌入图案类型的下电极（130）。

公开(公告)号：KR1020090017756A

公开(公告)日：2009-02-19

申请号：KR1020070082148

申请日：2007-08-16

申请人： 주식회사 심텍홀딩스

发明人： 오춘환 ,  정창보 ,  김태균 ,  박정권 ,  고영산 ,  이종태

IPC分类号： C09D1/00 ,  C09D161/12 ,  C09D161/00 ,  C09D183/04

CPC分类号： C09D1/00 ,  C08L63/00

摘要： A silver paste coating composition for a multilayer printed circuit board(PCB) build-up bump is provided to a film satisfying electrical characteristic of high reliability with excellent dispersibility and applicability and good adhesive property and electrode compact. A silver paste coating composition for a PCB build-up bump is obtained by mixing spherical type or flake type metal powder 70~90 weight%, resin 5~25 weight% selected from a group consisting of phenol materials, amino silane coupling agent 0.2~2 weight%, fumed silica 0.01~0.5 weight%, wetting dispersing agent 0.05~0.5 weight%, moisturizer 0.1~1.5 weight% and the remaining amount of butyl carbitol acetate, based on the total weight 100 weight%.

摘要翻译： 将具有优异的分散性和适用性以及良好的粘合性和电极小巧性的，具有高可靠性的电气特性的膜提供给多层印刷电路板（PCB）积聚凸块的银浆涂料组合物。 通过将70〜90重量％的球状或片状金属粉末，5〜25重量％的树脂，选自苯酚，氨基硅烷偶联剂，0.2〜 2重量％，热解法二氧化硅0.01〜0.5重量％，润湿分散剂0.05〜0.5重量％，保湿剂0.1〜1.5重量％，剩余量为丁基卡必醇乙酸酯，总重量为100重量％。

公开(公告)号：KR1020090017754A

公开(公告)日：2009-02-19

申请号：KR1020070082145

申请日：2007-08-16

申请人： 주식회사 심텍홀딩스

发明人： 오춘환 ,  정창보 ,  김태균 ,  박정권 ,  고영산 ,  이종태

IPC分类号： H05K3/46

CPC分类号： H05K3/4664 ,  H05K3/4007 ,  H05K2203/0338

摘要： A method for manufacturing of multilayer printed circuit board is provided to reduce the number of process and manufacturing cost without formation and copper electroplating hole with a mechanics or laser drill. A method for manufacturing of multilayer printed circuit board is comprised of the steps: forming the conductor bump on the fixed position of one page of the first copper foil(S10); penetrating the insulating layer which is the free plug-in(S20); laminating a first copper foil in which bump is formed by using the second copper foil is used for the upper dielectric layer(S30); performing circuit patterning to corresponded to the circuit design(S40).

摘要翻译： 提供了一种制造多层印刷电路板的方法，以减少不形成的工艺和制造成本，并且通过机械或激光钻孔减少铜电镀孔。 制造多层印刷电路板的方法包括以下步骤：在第一铜箔的一页的固定位置上形成导体凸块（S10）; 穿透作为自由插件的绝缘层（S20）; 层叠通过使用第二铜箔形成凸起的第一铜箔用于上电介质层（S30）; 执行电路图案化以对应于电路设计（S40）。