公开(公告)号：KR101892709B1

公开(公告)日：2018-08-28

申请号：KR1020120091799

申请日：2012-08-22

申请人： 에스케이하이닉스 주식회사

发明人： 박진철

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/10841 ,  H01L29/66666 ,  H01L29/7827

摘要： 본발명에따른반도체소자는주표면을갖는기판과, 제 1 도전영역, 제 2 도전영역및 상기제 1 도전영역과상기제 2 도전영역사이에구비되는채널영역을정의하며, 상기기판의주표면에대하여수직으로연장된제 1 필라와, 상기제 1 필라의상기채널영역상부에구비되는제 1 게이트와, 상기제 1 필라의하부에제 1 방향으로연장되고, 상기제 1 게이트에제 1 컨트롤시그널을제공하는매립워드라인및 상기제 1 컨트롤시그널이상기매립워드라인을통하여상기제 1 게이트에인가되도록제 1 게이트와매립워드라인을연결하는제 1 인터포저를포함하는것을특징으로한다.

公开(公告)号：KR1020140083745A

公开(公告)日：2014-07-04

申请号：KR1020120153821

申请日：2012-12-26

申请人： 에스케이하이닉스 주식회사

发明人： 조흥재 ,  황의성 ,  박은실

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10841 ,  H01L27/10864

摘要： Present technique relates to a semiconductor device having buried bit lines and a method for fabricating the same. The method of fabricating the semiconductor device according to the present invention includes the steps of burring a plurality of first punch preventing layers spaced apart from each other in a preliminary substrate; forming body lines on the first punch preventing layers, respectively, by etching the preliminary substrate; forming second punch preventing layers between the first punch preventing layers; and forming bit lines buried in the body lines. According to the present technology, after the first punch preventing layer is buried in the first trench, the body line is grown by growing an epitaxial layer to form a single crystalline body line having high quality. In addition, according to the present technology, the first punch preventing layer is formed under the buried bit line, and the second punch preventing layer is formed between the buried bit lines, so that the punch can be prevented between the neighboring buried bit lines.

摘要翻译： 现有技术涉及具有掩埋位线的半导体器件及其制造方法。 根据本发明的制造半导体器件的方法包括以下步骤：在预备衬底中翻开彼此间隔开的多个第一防冲击层; 通过蚀刻初步衬底分别在第一防冲击层上形成体线; 在所述第一防冲击层之间形成第二防冲击层; 并且形成埋在体线中的位线。 根据本技术，在将第一防冲击层埋设在第一沟槽中之后，通过生长外延层来生长体线以形成具有高质量的单晶体线。 此外，根据本技术，第一防冲击层形成在掩埋位线下方，并且第二防冲击层形成在掩埋位线之间，使得能够防止在相邻的掩埋位线之间的冲头。

公开(公告)号：KR1020140029052A

公开(公告)日：2014-03-10

申请号：KR1020120096717

申请日：2012-08-31

申请人： 에스케이하이닉스 주식회사

发明人： 조흥재

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/0688 ,  H01L27/10841 ,  H01L27/10885

摘要： The present technique provides a 3D semiconductor device capable of restraining a floating body effect of a vertical channel transistor and reducing a level of difficulty, and a method of manufacturing the same. The 3D semiconductor device includes a first semiconductor wafer including a first bonding layer; a second semiconductor wafer formed by stacking a vertical gate, a bit line and a second bonding layer on a semiconductor substrate, wherein the second bonding layer is bonded to the first bonding layer of the first semiconductor wafer, and the vertical gate includes source/drain areas and a vertical channel. The source area includes a semiconductor device serving as a charge trap layer. The semiconductor wafer on which the bit line is stacked is formed on the vertical gate. The semiconductor device is formed by using a wafer bonding scheme, so that the level of process difficulty is reduced. The source area of the vertical gate is formed as the charge trap layer, so that the floating body effect of the vertical gate and the refreshing property are improved.

摘要翻译： 本技术提供能够抑制垂直沟道晶体管的浮体效应并降低难度的3D半导体器件及其制造方法。 3D半导体器件包括：第一半导体晶片，其包括第一接合层; 通过在半导体衬底上堆叠垂直栅极，位线和第二接合层形成的第二半导体晶片，其中所述第二接合层接合到所述第一半导体晶片的所述第一接合层，并且所述垂直栅极包括源极/漏极 区域和垂直通道。 源区包括用作电荷陷阱层的半导体器件。 堆叠位线的半导体晶片形成在垂直栅极上。 通过使用晶片接合方式形成半导体器件，从而降低了工艺难度。 垂直栅极的源极区域形成为电荷陷阱层，从而提高了垂直栅极的浮体效应和刷新特性。

公开(公告)号：KR1020130103973A

公开(公告)日：2013-09-25

申请号：KR1020120025051

申请日：2012-03-12

申请人： 에스케이하이닉스 주식회사

发明人： 정우영

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/10885 ,  H01L27/10876 ,  H01L27/10841 ,  H01L27/10864

摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to reduce pillar floating body effects by securing a space margin in a pillar pattern with a bit line junction area of a vertical gate structure. CONSTITUTION: A plurality of pillar patterns (110) are formed on the upper side of a semiconductor substrate (100). Each pillar pattern includes one silicon pattern. A bit line junction area (130) is formed on the lower side of the pillar pattern. A bit line (150) is formed between the pillar patterns and is connected to the bit line junction area. A gate (160a) is formed on the sidewall of a pillar and is extended in a second direction which is vertical to the bit line. A storage electrode junction area (167) is formed on the upper side of the pillar pattern.

摘要翻译： 目的：提供一种半导体器件及其制造方法，以通过利用垂直栅极结构的位线接合区域确保柱状图案中的空间裕度来减少柱体浮体效应。 构成：在半导体衬底（100）的上侧形成多个柱状图案（110）。 每个支柱图案包括一个硅图案。 位线连接区域（130）形成在柱状图案的下侧。 位线（150）形成在柱状图案之间并连接到位线接合区域。 门（160a）形成在柱的侧壁上，并且在与位线垂直的第二方向上延伸。 存储电极接合区域（167）形成在柱状图案的上侧。

公开(公告)号：KR1020130103942A

公开(公告)日：2013-09-25

申请号：KR1020120024991

申请日：2012-03-12

申请人： 에스케이하이닉스 주식회사 ,  한국과학기술원

发明人： 문정민 ,  김태균 ,  이석희

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/10814 ,  H01L29/105 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7828 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885

摘要： PURPOSE: A semiconductor device including a vertical gate transistor without a junction and a manufacturing method thereof are provided to improve productivity by implanting one impurity to a source, a drain, and a body without the complexity of an impurity implantation process. CONSTITUTION: An active pillar (120) vertically protrudes from a substrate (110). The active pillar includes a first impurity region (120a), a second impurity region (120b), and a third impurity region (120c). The second impurity region is interposed between the first impurity region and the second impurity region. The first to third impurity regions include impurities with the same polarities. A gate electrode (160) is formed on the sidewall of the second impurity region. A bit line crosses the gate electrode and comes into contact with the first impurity region.

摘要翻译： 目的：提供一种包括没有结的垂直栅极晶体管及其制造方法的半导体器件，以通过将杂质注入到源极，漏极和器件中而不造成杂质注入工艺的复杂性来提高生产率。 构成：活性柱（120）从衬底（110）垂直突出。 有源支柱包括第一杂质区（120a），第二杂质区（120b）和第三杂质区（120c）。 第二杂质区位于第一杂质区和第二杂质区之间。 第一至第三杂质区域包括具有相同极性的杂质。 栅电极（160）形成在第二杂质区的侧壁上。 位线与栅电极交叉并与第一杂质区接触。

公开(公告)号：KR1020120052076A

公开(公告)日：2012-05-23

申请号：KR1020100113531

申请日：2010-11-15

申请人： 에스케이하이닉스 주식회사

发明人： 양희정

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/10841 ,  H01L29/66666

摘要： PURPOSE: A semiconductor device and a manufacturing method thereof are provided to increase the thickness of a gate oxide film arranged between a drain region and a gate metal layer, thereby preventing an electric field concentration phenomenon on an overlapping region between gates. CONSTITUTION: A vertical pillar(105) and a hard mask pattern(110) are formed on a substrate(100). A junction region is formed on the upper part of the vertical pillar. A first gate oxide film(130) is formed on the vertical pillar. A first metal layer(140) is formed on the first gate oxide film. A second gate oxide film(150) is formed on the first gate oxide film. A second metal layer(160) is formed on a second gate oxide film.

摘要翻译： 目的：提供一种半导体器件及其制造方法，以增加布置在漏极区域和栅极金属层之间的栅极氧化膜的厚度，从而防止栅极之间的重叠区域上的电场集中现象。 构成：在基板（100）上形成垂直柱（105）和硬掩模图案（110）。 在垂直柱的上部形成有接合区域。 第一栅极氧化膜（130）形成在垂直柱上。 第一金属层（140）形成在第一栅氧化膜上。 在第一栅极氧化膜上形成第二栅极氧化膜（150）。 第二金属层（160）形成在第二栅极氧化膜上。

公开(公告)号：KR1020120005685A

公开(公告)日：2012-01-17

申请号：KR1020100066268

申请日：2010-07-09

申请人： 에스케이하이닉스 주식회사

发明人： 김준기

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L21/2257 ,  H01L21/32 ,  H01L21/32134 ,  H01L21/32139 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/66666 ,  H01L27/10841

摘要： PURPOSE: A method for forming an etching barrier using a shadow effect and a method for manufacturing one side contact of a vertical transistor are provided to prevent an excessive impurity doping by depositing a doping barrier with a liner type. CONSTITUTION: Walls(101) are formed by a trench between semiconductor substrates(100). A surface of a semiconductor substrate is deposited with directivity in an incline direction. An etching barrier(400) is formed to expose one edge of a trench by a shadow effect.

摘要翻译： 目的：提供一种使用阴影效应形成蚀刻阻挡层的方法和用于制造垂直晶体管的一侧触点的方法，以通过沉积具有衬垫型的掺杂阻挡层来防止过量的杂质掺杂。 构成：壁（101）由半导体衬底（100）之间的沟槽形成。 以倾斜方向的方向性沉积半导体衬底的表面。 形成蚀刻阻挡层（400）以通过阴影效应来暴露沟槽的一个边缘。

公开(公告)号：KR1020100111130A

公开(公告)日：2010-10-14

申请号：KR1020090029536

申请日：2009-04-06

申请人： 에스케이하이닉스 주식회사

发明人： 김석구 ,  엄재철 ,  이상범

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L21/28282 ,  H01L27/10841 ,  H01L27/11273 ,  H01L27/11568 ,  H01L27/11582 ,  H01L29/513

摘要： PURPOSE: A vertical type nonvolatile memory device and a manufacturing method thereof are provided to enlarge a program and erase window with reducing the complexity of a conventional process. CONSTITUTION: A vertical type nonvolatile memory device includes a substrate(100), a first selection transistor layer(121), an electrode layer(141), and a second selection transistor layer(151). The first selection transistor layer is formed within the substrate. The electrode layer is repetitively formed by injecting an impurity ion by being separated from s separation layer formed by injecting an oxygen ion on the first selection transistor layer. The second selection transistor layer is formed by being separated from the separation layer on the electrode layer.

摘要翻译： 目的：提供一种垂直型非易失性存储器件及其制造方法，以便降低常规工艺的复杂度来扩大程序和擦除窗口。 构成：垂直型非易失性存储器件包括衬底（100），第一选择晶体管层（121），电极层（141）和第二选择晶体管层（151）。 第一选择晶体管层形成在衬底内。 通过从在第一选择晶体管层上注入氧离子而形成的分离层分离注入杂质离子来重复地形成电极层。 第二选择晶体管层通过与电极层上的分离层分离而形成。

公开(公告)号：KR1020100042904A

公开(公告)日：2010-04-27

申请号：KR1020080102113

申请日：2008-10-17

申请人： 에스케이하이닉스 주식회사

发明人： 홍기로

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L27/10876 ,  H01L27/10885 ,  H01L27/10841 ,  H01L27/10864

摘要： PURPOSE: A semiconductor device including a vertical gate and a manufacturing method thereof are provided to secure a dimension of a buried bit line process in a high integrated design rule below 3F^2. CONSTITUTION: A plurality of active pillars(36A) is formed on a substrate. A bulb type trench(38) is formed inside the substrate between the active pillars. A buried bit line(39A,39B) is buried in the sidewall of the bulb type trench. A plurality of active pillars is formed by etching a preliminary active pillar. The vertical gate surrounds the sidewall of the active pillar.

摘要翻译： 目的：提供一种包括垂直栅极及其制造方法的半导体器件，用于将埋入式位线工艺的尺寸确保在低于3F ^ 2的高集成设计规则中。 构成：在衬底上形成多个活性柱（36A）。 在活性柱之间的衬底内部形成有灯泡型沟槽（38）。 掩埋位线（39A，39B）埋在灯泡型沟槽的侧壁中。 通过蚀刻预活性柱来形成多个活性柱。 垂直门围绕有源柱的侧壁。

公开(公告)号：KR1020090126339A

公开(公告)日：2009-12-09

申请号：KR1020080052368

申请日：2008-06-04

申请人： 삼성전자주식회사

发明人： 손용훈 ,  이종욱 ,  강종혁

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841 ,  H01L27/10841

摘要： PURPOSE: A vertical type semiconductor device, a method for manufacturing the same and a method for operating the same are provided to enhance the integration degree of device by storing the data in the channel region of the single-crystal semiconductor pattern. CONSTITUTION: A pillar shaped single-crystal semiconductor pattern(118) is included in the top of the substrate. The gate wraps the sidewall of the single-crystal semiconductor pattern. The upper side of the gate is lower than the upper side of the single-crystal semiconductor pattern. The mask pattern(110a) is laminated in the gate upper side. The upper side of the mask pattern is located on the same plane as the upper side of the single-crystal semiconductor pattern. The first impurity region(104) is located on the substrate under the single-crystal semiconductor pattern. The second impurity region is located under the upper side of the single-crystal semiconductor pattern.

摘要翻译： 目的：提供垂直型半导体器件及其制造方法及其操作方法，以通过将数据存储在单晶半导体图案的沟道区域来提高器件的集成度。 构成：在基板的顶部包括柱形单晶半导体图案（118）。 栅极包裹单晶半导体图案的侧壁。 栅极的上侧比单晶半导体图案的上侧低。 掩模图案（110a）层叠在栅极上侧。 掩模图案的上侧位于与单晶半导体图案的上侧相同的平面上。 第一杂质区（104）位于单晶半导体图案下的衬底上。 第二杂质区位于单晶半导体图案的上侧的下方。