公开(公告)号：US20140089748A1

公开(公告)日：2014-03-27

申请号：US13624706

申请日：2012-09-21

申请人： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

发明人： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

IPC分类号： G01R31/3177

CPC分类号： G01R31/31705

摘要： Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.

摘要翻译： 描述了用于热插拔调试器功能的系统和技术。 所描述的集成电路设备包括处理器，第一焊盘接口，经配置以经由第一焊盘接口检测时钟信号的检测器，一个或多个第二焊盘接口，两个或多个部件，包括与处理器通信耦合的调试系统 ，多路通信地与所述一个或多个第二焊盘接口和所述两个或更多个部件耦合，并且被配置为选择性地将所述一个或多个第二焊盘接口与所述两个或更多个部件的选定部件相互连接。 当通过第一焊盘接口检测到时钟信号时，多路复用器可被配置为使调试系统成为所选择的部件。

公开(公告)号：US08726223B2

公开(公告)日：2014-05-13

申请号：US13624706

申请日：2012-09-21

申请人： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

发明人： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

IPC分类号： G06F17/50

CPC分类号： G01R31/31705

摘要： Systems and techniques for hot-plugging debugger capabilities are described. A described integrated circuit device includes a processor, a first pad interface, a detector configured to detect a clock signal via the first pad interface, one or more second pad interfaces, two or more components including a debug system that is communicatively coupled with the processor, a multiplexer communicatively coupled with the one or more second pad interfaces and the two or more components, and configured to selectively interconnect the one or more second pad interfaces with a selected component of the two or more components. The multiplexer can be configured to cause the debug system to be the selected component when the clock signal is detected via the first pad interface.

摘要翻译： 描述了用于热插拔调试器功能的系统和技术。 所描述的集成电路设备包括处理器，第一焊盘接口，经配置以经由第一焊盘接口检测时钟信号的检测器，一个或多个第二焊盘接口，两个或多个部件，包括与处理器通信耦合的调试系统 ，多路通信地与所述一个或多个第二焊盘接口和所述两个或更多个部件耦合，并且被配置为选择性地将所述一个或多个第二焊盘接口与所述两个或更多个部件的选定部件相互连接。 当通过第一焊盘接口检测到时钟信号时，多路复用器可被配置为使调试系统成为所选择的部件。

公开(公告)号：US20140089648A1

公开(公告)日：2014-03-27

申请号：US13624651

申请日：2012-09-21

申请人： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

发明人： Sylvain Garnier ,  Anthony Rouaux ,  Sebastien Jouin ,  Frode Milch Pedersen

IPC分类号： G06F1/24

CPC分类号： G06F1/24 ,  G06F11/267

摘要： Systems and techniques for processor reset hold control are described. A described system includes a controller to detect a hold request based on an external reset signal and an external debug signal, and generate a hold signal based on a detection of the hold request, where the hold signal continues after the external reset signal has been discontinued; a system component that is responsive to the external reset signal; a processor that is responsive to the hold signal, where the hold signal causes the processor to enter a reset state and to maintain the reset state after the external reset signal has been discontinued; and a system manager configured to permit external access to the system component while the processor is in the reset state. The controller can be configured to discontinue the hold signal in response to a clear request.

摘要翻译： 描述了处理器复位保持控制的系统和技术。 所描述的系统包括控制器，用于基于外部复位信号和外部调试信号检测保持请求，并且基于对保持信号的检测产生保持信号，其中保持信号在外部复位信号已经中断之后继续 ; 响应于外部复位信号的系统组件; 响应于所述保持信号的处理器，其中所述保持信号使所述处理器进入复位状态，并且在所述外部复位信号已经中断之后保持所述复位状态; 以及被配置为在处理器处于复位状态时允许对系统组件的外部访问的系统管理器。 控制器可以被配置为响应于明确的请求中断保持信号。