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公开(公告)号：US08378714B2
公开(公告)日：2013-02-19
申请号：US12829087
申请日：2010-07-01
IPC: H03K19/094
CPC classification number: H03F3/45183 , H01L2924/0002 , H03F3/45188 , H03F3/45632 , H03F2203/45101 , H01L2924/00
Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads. Further provided is a bias isolating circuit so that an input bias voltage is isolated from a high voltage in the pads.
Abstract translation: 提供了工作在低电压下的高耐压收发器，包括用于接收接收信号并传输发射信号的两个输入/输出焊盘; 用于发送所述发送信号的发送器模块; 接收器块，用于接收接收信号并提供放大信号; 发射机模块和接收机模块中的至少一个进一步包括至少两个NMOS晶体管，其栅极耦合到低电源以接收低电压，它们的衬底耦合到地，并且它们的源耦合到输入/输出焊盘。 还提供了用于将发射器的输出与包括第一晶体管和第二晶体管的高电压隔离的电路。 还提供了一种衬底隔离电路，其包括第一晶体管，第二晶体管和第三晶体管，使得衬底电压与衬垫中的高电压隔离。 还提供了一种偏置隔离电路，使得输入偏置电压与焊盘中的高电压隔离。
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公开(公告)号：US20120001671A1
公开(公告)日：2012-01-05
申请号：US12829087
申请日：2010-07-01
CPC classification number: H03F3/45183 , H01L2924/0002 , H03F3/45188 , H03F3/45632 , H03F2203/45101 , H01L2924/00
Abstract: A high voltage tolerant transceiver operating at a low voltage is provided, including two input/output pads to receive a receive signal and transmit a transmit signal; a transmitter block to transmit the transmit signal; a receiver block to receive the receive signal and provide an amplified signal; at least one of the transmitter block and the receiver block further comprising at least two NMOS transistors having their gate coupled to a low power supply to receive the low voltage, their substrate coupled to ground, and their source coupled to the input/output pad. Also provided is a circuit to isolate the output of a transmitter from high voltages, including a first transistor and a second transistor. Also provided is a substrate isolating circuit, including a first transistor, a second transistor, and a third transistor so that the substrate voltage is isolated from a high voltage in the pads. Further provided is a bias isolating circuit so that an input bias voltage is isolated from a high voltage in the pads.
Abstract translation: 提供了工作在低电压下的高耐压收发器，包括用于接收接收信号并传输发射信号的两个输入/输出焊盘; 用于发送所述发送信号的发送器模块; 接收器块，用于接收接收信号并提供放大信号; 发射机模块和接收机模块中的至少一个进一步包括至少两个NMOS晶体管，其栅极耦合到低电源以接收低电压，它们的衬底耦合到地，并且其源极耦合到输入/输出焊盘。 还提供了用于将发射器的输出与包括第一晶体管和第二晶体管的高电压隔离的电路。 还提供了一种衬底隔离电路，其包括第一晶体管，第二晶体管和第三晶体管，使得衬底电压与衬垫中的高电压隔离。 还提供了一种偏置隔离电路，使得输入偏置电压与焊盘中的高电压隔离。
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公开(公告)号：US07382591B2
公开(公告)日：2008-06-03
申请号：US11133648
申请日：2005-05-20
Applicant: Bi Han , Daniel Chu , Mase Taub
Inventor： Bi Han , Daniel Chu , Mase Taub
IPC: H02H9/00
CPC classification number: G11C16/12 , G11C16/30 , Y10T307/964
Abstract: A double cascode protected switchable voltage source may be used to selectively provide positive or negative voltage sources, for example, to a flash memory. The positive supply may be connected through a PMOS pass device to a first cascode protection device. A negative supply may be connected through an NMOS pass device and an NMOS cascode protection device to an output. The circuits may be designed so that exceeding snapback limits and gate aided drain breakdown are less likely.
Abstract translation: 可以使用双共源共栅保护的可切换电压源来选择性地将正或负电压源例如提供给闪存。 正电源可以通过PMOS通道器件连接到第一共源共栅保护器件。 负电源可以通过NMOS通道器件和NMOS共源共栅保护器件连接到输出端。 这些电路可以被设计成使得超过回跳限制和栅极辅助漏极击穿不太可能。
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公开(公告)号：US20060267414A1
公开(公告)日：2006-11-30
申请号：US11133648
申请日：2005-05-20
Applicant: Bi Han , Daniel Chu , Mase Taub
Inventor： Bi Han , Daniel Chu , Mase Taub
IPC: H01H3/34
CPC classification number: G11C16/12 , G11C16/30 , Y10T307/964
Abstract: A double cascode protected switchable voltage source may be used to selectively provide positive or negative voltage sources, for example, to a flash memory. The positive supply may be connected through a PMOS pass device to a first cascode protection device. A negative supply may be connected through an NMOS pass device and an NMOS cascode protection device to an output. The circuits may be designed so that exceeding snapback limits and gate aided drain breakdown are less likely.
Abstract translation: 可以使用双共源共栅保护的可切换电压源来选择性地将正或负电压源例如提供给闪存。 正电源可以通过PMOS通道器件连接到第一共源共栅保护器件。 负电源可以通过NMOS通道器件和NMOS共源共栅保护器件连接到输出端。 这些电路可以被设计成使得超过回跳限制和栅极辅助漏极击穿不太可能。
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