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公开(公告)号：US20240363173A1
公开(公告)日：2024-10-31
申请号：US18768091
申请日：2024-07-10
申请人： Intel NDTM US LLC
发明人： Narayanan RAMANAN
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/30 , G11C16/3427
摘要： Modulation of the source voltage in a NAND-flash array read waveform can enable improved read-disturb mitigation. For example, increasing the source line voltage to a voltage with a magnitude greater than the non-idle source voltage during the read operation when the array is idle (e.g., not during sensing) enables a reduction in read disturb without the complexity arising from the consideration of multiple read types. Additional improvement in FN disturb may also be obtained on the sub-blocks in the selected SGS by increasing the source line voltage during the selected wordline ramp when the array is idle.
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公开(公告)号：US20240363168A1
公开(公告)日：2024-10-31
申请号：US18230336
申请日：2023-08-04
发明人： Abhijith Prakash , Xiang Yang
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
摘要： The memory device includes a chip with at least one voltage pump and a plurality of planes. The planes have arrays of memory cells that can be programmed and erased. At least some of the planes are at different distances from the at least one voltage pump. The memory device further includes control circuitry that is configured to program and erase the memory cells. The control circuitry is further configured to supply at least one voltage to a selected plane of the plurality of planes during a programming operation or an erase pulse and adjust the at least one voltage that is supplied to the selected plane by a parameter that is determined based on a distance between the selected plane and the at least one voltage pump.
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公开(公告)号：US12125540B2
公开(公告)日：2024-10-22
申请号：US17733474
申请日：2022-04-29
CPC分类号： G11C16/102 , G11C16/22 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3404
摘要： Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.
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公开(公告)号：US12125532B2
公开(公告)日：2024-10-22
申请号：US17459172
申请日：2021-08-27
发明人： Laurent Murillo
CPC分类号： G11C16/0433 , G11C16/102 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/30
摘要： In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.
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5.发明公开公开(公告)号：US20240331774A1
公开(公告)日：2024-10-03
申请号：US18367677
申请日：2023-09-13
发明人： Gangmin Lee , Jaehue Shin , Daeseok Byeon , Yongsung Cho
CPC分类号： G11C16/0491 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/30 , G11C29/10
摘要： A nonvolatile memory device may include a page buffer, a control signal generator, and a current mirror. The page buffer may be connected to a bitline and may allow a replicated current to flow through a ground terminal in response to a first control signal and a second control signal. The control signal generator may output the first control signal and the second control signal to the page buffer. The current mirror may output, in a virtual cell mode, a control voltage corresponding to a bias current. The control voltage may correspond to the first control signal.
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公开(公告)号：US12106811B2
公开(公告)日：2024-10-01
申请号：US17882459
申请日：2022-08-05
申请人： Kioxia Corporation
发明人： Yousuke Hagiwara , Kei Shiraishi
CPC分类号： G11C16/32 , G11C16/0483 , G11C16/26 , G11C16/30
摘要： A semiconductor memory device includes a comparator that outputs a signal switched in synchronism with a read enable signal from outside and outputs the signal, and a correction circuit that adjusts the duty cycle of the signal. The correction circuit includes a variable current source connected to a first output portion of the comparator, and a variable current source connected to a second output portion of the comparator, and adjusts the amounts of current output from the current sources to adjust the duty cycles of signals.
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公开(公告)号：US12106808B2
公开(公告)日：2024-10-01
申请号：US18485630
申请日：2023-10-12
申请人： Kioxia Corporation
发明人： Mai Shimizu , Koji Kato , Yoshihiko Kamata , Mario Sako
IPC分类号： G11C16/08 , G11C11/56 , G11C16/04 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/34
CPC分类号： G11C16/08 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3427
摘要： A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US12094543B2
公开(公告)日：2024-09-17
申请号：US17703998
申请日：2022-03-25
发明人： Chung-Zen Chen
摘要： A memory and a sense amplifying device are provided. The sense amplifying device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal to receive a data signal and a reference signal, respectively. The first pre-charge circuit is coupled to the first input terminal of the differential amplifier. The first pre-charge circuit, based on a power voltage, performs a pre-charge operation on the first input terminal of the differential amplifier according to a pre-charge enable signal and a control voltage. The control voltage generator generates the control voltage according to the power voltage, and the control voltage and the power voltage are in a positive correlation.
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公开(公告)号：US20240290396A1
公开(公告)日：2024-08-29
申请号：US18444448
申请日：2024-02-16
发明人： Liang Yu , Jonathan S. Parry , Tal Sharifie
CPC分类号： G11C16/30 , G06F12/0246
摘要： Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.
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公开(公告)号：US12073891B2
公开(公告)日：2024-08-27
申请号：US17682089
申请日：2022-02-28
发明人： Eric N. Lee , Violante Moschiano , Jeffrey S. McNeil , James Fitzpatrick , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Patrick R. Khayat
CPC分类号： G11C16/30 , G11C16/102 , G11C16/26 , G11C2207/2254
摘要： Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.
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