公开(公告)号：US06772311B2

公开(公告)日：2004-08-03

申请号：US10179146

申请日：2002-06-24

申请人： Brian Tse Deng

发明人： Brian Tse Deng

IPC分类号： G06F1300

CPC分类号： G06F13/385

摘要： A controller that supports both aligned and unaligned PIO data transfers associated with ATAPI devices in a fashion that reduces command overhead to improve ATAPI device system performance. A 32-bit wide sector FIFO, implemented with a 32-bit single port RAM using read and write pointer control logic, is used to store packet data transmitted to and received from the other data bus (i.e. USB). The 32-bit single port RAM functions as a FIFO to allow both the USB side and the ATAPI side to simultaneously access the sector FIFO.

摘要翻译： 支持与ATAPI设备相关联的对齐和未对齐的PIO数据传输的控制器，以减少命令开销来提高ATAPI设备系统性能。 使用32位单端口RAM使用读写指针控制逻辑实现的32位宽扇区FIFO用于存储发送到其他数据总线（即USB）并从其它数据总线（即USB）接收的数据包数据。 32位单端口RAM用作FIFO，以允许USB端和ATAPI端同时访问扇区FIFO。

公开(公告)号：US07512148B2

公开(公告)日：2009-03-31

申请号：US10731810

申请日：2003-12-09

申请人： Stephen Li ,  Brian Tse Deng

发明人： Stephen Li ,  Brian Tse Deng

IPC分类号： H04J3/02

CPC分类号： H04L12/56

摘要： A weighted round-robin arbitrator for a plurality of data queue includes an arbitration table comprising a plurality of entries. Each entry represents a time slot for the transmission of one data packet from a selected one of the plurality of data queues. There is one arbitration logic circuit for each of the plurality of entries in the arbitration table. Each arbitration logic circuit includes a first multiplexer receiving an output from a first table entry and an output from a second table entry in the arbitration table. A second multiplexer receives empty flags from each of the data queues, the flags indicating that there is no data to the sent from that queue. An output of the second multiplexer is coupled to a control input of the first multiplexer so that the first table entry value is output from the first multiplexer if the corresponding queue has data to be sent out and the second table entry value is sent out from the first multiplexer if the queue corresponding to that table entry has data to be sent out and the queue corresponding to the first entry has no data to be sent out.

摘要翻译： 用于多个数据队列的加权轮询仲裁器包括包括多个条目的仲裁表。 每个条目表示用于从多个数据队列中选择的一个数据队列传输一个数据包的时隙。 仲裁表中的多个条目中的每一个都有一个仲裁逻辑电路。 每个仲裁逻辑电路包括接收来自第一表条目的输出的第一多路复用器和仲裁表中的第二表条目的输出。 第二个多路复用器从每个数据队列接收空标志，标志指示从该队列发送的数据没有数据。 第二多路复用器的输出被耦合到第一多路复用器的控制输入，使得如果对应的队列具有要发送的数据并且从第一多路复用器发送第二表输入值，则从第一多路复用器输出第一表条目值 第一复用器如果对应于该表项的队列具有要发送的数据，并且对应于第一条目的队列没有要发送的数据。

公开(公告)号：US5815509A

公开(公告)日：1998-09-29

申请号：US934156

申请日：1997-09-19

申请人： Brian Tse Deng ,  Henry N. Angulo ,  Bob Gugel

发明人： Brian Tse Deng ,  Henry N. Angulo ,  Bob Gugel

IPC分类号： G06F12/16 ,  G06F13/00 ,  G11C7/00 ,  G11C29/00 ,  G11C29/14 ,  H04L12/40 ,  H04L12/64 ,  G06F11/00

CPC分类号： H04L12/40123 ,  G11C29/003 ,  G11C29/14

摘要： The invention comprises a method and system for testing memory in an interface system 10 coupling a parallel host bus 30 to a serial bus 20. The system comprises a random access memory 70 having a plurality of memory locations for temporarily storing data received from either the parallel host bus 30 or the IEEE 1394 serial bus 20, the random access memory 70 being logically divided into a transmit memory portion and a receive memory portion. The interface also comprises a transmission control unit 40 operable to control transmission of data from the parallel host bus 30 to the IEEE 1394 serial bus 20. The transmission control unit 40 is further operable to access the transmit memory portion of the random access memory 70. The interface also comprises a reception control unit 50 operable to control reception of data by the parallel bus 30 from the serial bus 20. The receive control unit 50 is further operable to access the receive memory portion of the random access memory 70. The interface further comprises a test unit 60 operable to selectively obtain control of the random access memory 70 based on a control signal received from the parallel host bus 30; internally generate addresses for each memory location within the random access memory 70; control transmission of parallel data from each memory location associated with the internally generated addresses to the parallel host bus 30 for inspection; and selectively relinquish control of the random access memory 70 to allow transmission of data between the IEEE 1394 serial bus 20 and the parallel host bus 30.

摘要翻译： 本发明包括用于在将并行主机总线30耦合到串行总线20的接口系统10中测试存储器的方法和系统。该系统包括具有多个存储器位置的随机存取存储器70，用于临时存储从并行 主机总线30或IEEE 1394串行总线20，随机存取存储器70在逻辑上被划分为发送存储器部分和接收存储器部分。 接口还包括传输控制单元40，其可操作以控制从并行主机总线30到IEEE 1394串行总线20的数据传输。传输控制单元40还可操作以访问随机存取存储器70的传输存储器部分。 该接口还包括接收控制单元50，其可操作以控制并行总线30从串行总线20接收数据。接收控制单元50还可操作以访问随机存取存储器70的接收存储器部分。接口进一步 包括测试单元60，其可操作以基于从并行主机总线30接收的控制信号选择性地获得对随机存取存储器70的控制; 内部为随机存取存储器70内的每个存储单元生成地址; 控制从与内部产生的地址相关联的每个存储器位置将并行数据传输到并行主机总线30进行检查; 并且选择性地放弃对随机存取存储器70的控制以允许IEEE 1394串行总线20和并行主机总线30之间的数据传输。

公开(公告)号：US07010638B2

公开(公告)日：2006-03-07

申请号：US10651524

申请日：2003-08-29

申请人： Brian Tse Deng ,  Dinghui Richard Nie ,  Joseph M. Erickson

发明人： Brian Tse Deng ,  Dinghui Richard Nie ,  Joseph M. Erickson

IPC分类号： G06F13/00 ,  G06F13/36

CPC分类号： G06F13/385

摘要： A bridge controller controls the data flow to/from a USB bus to/from an ATA/ATAPI drive, such as an ATA hard drive or ATAPI CD or DVD drive. The bridge controller has a state machine which receives the CBW in a background mode in real time as the packet is being transferred to the bridge controller. The state machine uses the CBW to set up the data transfer. The bridge controller also has a programmable processor which is coupled to the CBW once it is received in a buffer memory. The programmable processor makes changes in the set up of the receiving device for the transfer, if needed, and initiates the data transfer.

摘要翻译： 桥接控制器控制往返于ATA / ATAPI驱动器的USB总线的数据流，例如ATA硬盘驱动器或ATAPI CD或DVD驱动器。 桥控制器具有状态机，当分组被传送到桥控制器时，实时地以后台模式接收CBW。 状态机使用CBW设置数据传输。 桥接控制器还具有可编程处理器，一旦它被接收在缓冲存储器中，它就耦合到CBW。 如果需要，可编程处理器对接收设备的设置进行改变，并发起数据传输。

公开(公告)号：US06915416B2

公开(公告)日：2005-07-05

申请号：US09752567

申请日：2000-12-28

申请人： Brian Tse Deng ,  Jian Yu ,  Fengchun Duan

发明人： Brian Tse Deng ,  Jian Yu ,  Fengchun Duan

IPC分类号： G06F11/36 ,  G06F13/24

CPC分类号： G06F11/3644

摘要： Apparatus and method for microcontroller debugging. A preferred embodiment microcontroller integrated circuit comprises debug circuitry on the integrated circuit. The debug circuitry is capable of breaking normal instruction execution based on an address breakpoint, a stack pointer breakpoint, or a single step breakpoint. Upon detection of a valid breakpoint, the debug circuitry substitutes a jump to a debug program instruction in place of the next normal application program instruction. The debug program then may provide microcontroller status to a developer, allowing the developer to debug the application program. Upon completion of the debug program, control of the microcontroller is returned to the application program at the point of interruption.

摘要翻译： 微控制器调试的装置和方法 优选实施例微控制器集成电路包括集成电路上的调试电路。 调试电路能够基于地址断点，堆栈指针断点或单个步骤断点来中断正常指令执行。 在检测到有效的断点时，调试电路代替下一个正常应用程序指令的跳转代替调试程序指令。 然后，调试程序可以向开发人员提供微控制器状态，允许开发人员调试应用程序。 完成调试程序后，微控制器的控制在中断点返回到应用程序。

公开(公告)号：US06539448B1

公开(公告)日：2003-03-25

申请号：US09580810

申请日：2000-05-26

申请人： Brian Tse Deng

发明人： Brian Tse Deng

IPC分类号： G06F1324

CPC分类号： G06F13/26

摘要： A microprocessor interrupt controller capable of receiving a plurality of interrupt requests organized in a plurality of groups, at least one of the groups including a plurality of interrupt requests, and providing the interrupts requests to a microprocessor. The controller includes a plurality of storage units corresponding to the plurality of groups and capable of storing one or more of the interrupt requests, by group, and providing the interrupt requests so stored as outputs, on a first in first out basis. At least one write arbiter unit is also included, associated with the storage unit for the at least one of the groups including a plurality of interrupt requests, for providing simultaneously pending interrupt requests of the at least one of the groups to the associated storage unit on a priority basis. A priority encoder unit is included for receiving the interrupt requests stored in the storage units and providing the interrupt requests as outputs for processing by the microprocessor, on a priority basis.

摘要翻译： 一种微处理器中断控制器，其能够接收组织在多个组中的多个中断请求，所述组中的至少一个包括多个中断请求，并且向微处理器提供中断请求。 所述控制器包括与所述多个组对应的多个存储单元，并能够按照一组存储一个或多个所述中断请求，并且提供如此存储为输出的所述中断请求。 还包括与包括多个中断请求的组中的至少一个的存储单元相关联的至少一个写入仲裁器单元，用于将组中的至少一个的同时待决的中断请求提供给相关联的存储单元 优先依据。 包括优先编码器单元，用于接收存储在存储单元中的中断请求，并且提供中断请求作为微处理器优先处理的输出作为输出。