公开(公告)号：US06174777B1

公开(公告)日：2001-01-16

申请号：US09383596

申请日：1999-08-26

申请人： Dowson Jang

发明人： Dowson Jang

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/76885

摘要： This invention provides a method for forming a self aligned contact using a reverse self aligned contact etch process. A substrate structure is provided having conductive structures thereon. The conductive structures can be any of a number of structures including, but not limited to: floating gate transistors, capacitors, word lines, or a combination thereof. The substrate structure also has doped regions thereon adjacent to one or both sides of the conductive structures. A polysilicon layer is formed over the conductive structures and the doped regions. A photoresist mask is formed over the polysilicon layer having openings over the conductive structures. The polysilicon layer is etched through the openings in the photoresist mask and stopping on the hard masks to form self aligned contacts over the doped regions. A dielectric layer is formed over the self aligned contacts and the conductive structures. The dielectric layer and the self aligned contacts are planarized.

摘要翻译： 本发明提供使用反向自对准接触蚀刻工艺形成自对准接触的方法。 提供其上具有导电结构的衬底结构。 导电结构可以是许多结构中的任何一种，包括但不限于：浮栅晶体管，电容器，字线或其组合。 衬底结构还具有与导电结构的一侧或两侧相邻的掺杂区域。 在导电结构和掺杂区上方形成多晶硅层。 在具有在导电结构上的开口的多晶硅层上形成光致抗蚀剂掩模。 通过光致抗蚀剂掩模中的开口蚀刻多晶硅层，并停止在硬掩模上以在掺杂区域上形成自对准接触。 在自对准的触点和导电结构之上形成介电层。 介电层和自对准触点被平坦化。

公开(公告)号：US5915202A

公开(公告)日：1999-06-22

申请号：US857161

申请日：1997-05-15

申请人： Chi-Hsin Lo ,  Dowson Jang ,  Woei-Ji Song

发明人： Chi-Hsin Lo ,  Dowson Jang ,  Woei-Ji Song

IPC分类号： H01L21/321 ,  H01L21/3213 ,  H01L21/461

CPC分类号： H01L21/32115 ,  H01L21/32136

摘要： An improved and new method of forming tungsten plugs on contact holes in semiconductor integrated circuit devices has been developed. The method uses a two step tungsten etchback process wherein redeposition of etch byproducts is surpressed, residue removal is enhanced, and the overetching requirement is reduced. The result is a more reliable, lower cost, higher yield process.

摘要翻译： 已经开发了一种在半导体集成电路器件的接触孔上形成钨插塞的改进和新的方法。 该方法使用两步钨回蚀工艺，其中蚀刻副产物的再沉积被抑制，残余物去除被增强，并且过蚀刻要求降低。 结果是更可靠，更低成本，更高的产量过程。

公开(公告)号：US06740471B1

公开(公告)日：2004-05-25

申请号：US10101658

申请日：2002-03-20

申请人： Gau-Ming Lu ,  Dowson Jang ,  Wen-Han Hung ,  Yeong-Rong Chang

发明人： Gau-Ming Lu ,  Dowson Jang ,  Wen-Han Hung ,  Yeong-Rong Chang

IPC分类号： G03F742

CPC分类号： G03F7/16 ,  H01L21/0274 ,  Y02P80/30

摘要： A method of improving photoresist adhesion in a reworked device, including the following steps. A semiconductor structure having an upper exposed metal layer is provided. An ARC layer is formed over the upper exposed metal layer. The ARC layer having an upper surface. A first photoresist layer is formed upon the ARC layer. The first photoresist layer is removed by a rework process. The ARC layer upper surface is roughened to form a roughened ARC layer upper surface. A second photoresist layer is formed upon the roughened ARC layer upper surface whereby adhesion of the second photoresist layer to the ARC layer is improved.

摘要翻译： 一种改善返工装置中的光致抗蚀剂粘附性的方法，包括以下步骤。 提供具有上暴露金属层的半导体结构。 在上部暴露的金属层上形成ARC层。 ARC层具有上表面。 在ARC层上形成第一光致抗蚀剂层。 通过返工工艺去除第一光致抗蚀剂层。 ARC层上表面被粗糙化以形成粗糙化的ARC层上表面。 第二光致抗蚀剂层形成在粗糙化的ARC层上表面上，从而提高了第二光致抗蚀剂层与ARC层的粘附。

公开(公告)号：US5755891A

公开(公告)日：1998-05-26

申请号：US789214

申请日：1997-01-24

申请人： Chi-Hsin Lo ,  Dowson Jang ,  Hsueh-Liang Chiu

发明人： Chi-Hsin Lo ,  Dowson Jang ,  Hsueh-Liang Chiu

IPC分类号： B08B7/00 ,  B08B6/00 ,  H01L21/302

CPC分类号： B08B7/0035

摘要： An improved process is described for the post-etching treatment after subtractive etching of aluminum and aluminum-alloy layers in the fabrication of semiconductor integrated circuit devices. The improvement consists of in situ exposure immediately after subtractive etching of the metal pattern to a reactive plasma sustained in a mixture of oxygen and carbon tetrafluoride gases by continuous radiofrequency power input for a controlled period of time.

摘要翻译： 对在半导体集成电路器件的制造中对铝和铝合金层进行减蚀蚀后的后蚀刻处理进行了描述。 该改进包括在通过连续的射频功率输入在受控时间段内将金属图案减去蚀刻到氧气和四氟化碳气体的混合物中的反应性等离子体之后立即曝光。