公开(公告)号：US20240228830A1

公开(公告)日：2024-07-11

申请号：US17928395

申请日：2022-07-19

Applicant: Showa Denko Materials Co., Ltd.

Inventor： Hiroshi ONO ,  Keisuke INOUE ,  Takahiro JINUSHI

IPC: C09G1/02 ,  B24B37/04 ,  C09K3/14 ,  H01L21/321

CPC classification number: C09G1/02 ,  B24B37/044 ,  C09K3/1409 ,  H01L21/32115

Abstract: A polishing liquid for polishing a surface to be polished containing a tungsten material, the polishing liquid containing abrasive grains, an iron-containing compound, and an oxidizing agent, in which the abrasive grains include silica particles, an average particle diameter of the abrasive grains is 40 to 140 nm, and a silanol group density of the silica particles is 8.0 groups/nm2 or less. A polishing method of polishing a surface to be polished containing a tungsten material by using the polishing liquid.

公开(公告)号：US20240038548A1

公开(公告)日：2024-02-01

申请号：US18377422

申请日：2023-10-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： YING-CHENG CHUANG

IPC: H01L21/3213 ,  H01L21/027 ,  H01L21/321 ,  H01L21/762

CPC classification number: H01L21/32139 ,  H01L21/0274 ,  H01L21/32115 ,  H01L21/76224

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

公开(公告)号：US20230386858A1

公开(公告)日：2023-11-30

申请号：US17828802

申请日：2022-05-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： YING-CHENG CHUANG

IPC: H01L21/3213 ,  H01L21/321 ,  H01L21/027 ,  H01L21/762

CPC classification number: H01L21/32139 ,  H01L21/32115 ,  H01L21/0274 ,  H01L21/76224

Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.

公开(公告)号：US11756833B2

公开(公告)日：2023-09-12

申请号：US17738968

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Matthew J. Prince

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/768 ,  H01L23/498 ,  H01L23/532 ,  H01L23/535 ,  H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L21/823437 ,  H01L21/31053 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823475 ,  H01L23/49838 ,  H01L23/535 ,  H01L23/5329 ,  H01L24/16 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/42372 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes forming a plurality of lines, wherein individual lines of the plurality of lines comprise a gate electrode material, depositing an electrically insulative material to fill regions between the individual lines and subsequent to depositing the electrically insulative material, removing a portion of at least one of the individual lines to isolate gate electrode material of a first transistor device from gate electrode material of a second transistor device. Other embodiments may be described and/or claimed.

公开(公告)号：US10366926B1

公开(公告)日：2019-07-30

申请号：US16390246

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321

CPC classification number: H01L21/823431 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32115 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

公开(公告)号：US20190221423A1

公开(公告)日：2019-07-18

申请号：US15869258

申请日：2018-01-12

Applicant: International Business Machines Corporation

Inventor： Ekmini A. De Silva ,  Nelson Felix ,  Jing Guo ,  Indira Seshadri

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/321 ,  H01L29/49 ,  G03F7/09

CPC classification number: H01L21/02074 ,  G03F7/091 ,  G03F7/094 ,  H01L21/28088 ,  H01L21/32115 ,  H01L29/0649 ,  H01L29/4966 ,  H01L29/7851

Abstract: Embodiments of the present invention are directed to the wet stripping of an organic planarization layer (OPL) using reversible UV crosslinking and de-crosslinking. In a non-limiting embodiment of the invention, an interlayer dielectric is formed over a substrate. A trench is formed in the interlayer dielectric. A work function metal is formed over the interlayer dielectric such that a portion of the work function metal partially fills the trench. A UV sensitive OPL is formed over the work function metal such that a portion of the UV sensitive OPL fills the trench. The UV sensitive OPL can be crosslinked by applying light at a first UV frequency and de-crosslinked by applying light at a second UV frequency.

公开(公告)号：US20190027513A1

公开(公告)日：2019-01-24

申请号：US15575054

申请日：2017-08-01

Applicant: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY

Inventor： Leilei Dong

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/1274 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02664 ,  H01L21/02675 ,  H01L21/02686 ,  H01L21/3065 ,  H01L21/32115 ,  H01L27/1222 ,  H01L27/3262 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78675

Abstract: The present disclosure discloses a manufacturing method of a polycrystalline silicon thin film, which includes: forming a first amorphous silicon thin film; crystallizing the first amorphous silicon thin film to form a polycrystalline silicon thin film by applying an excimer laser annealing process; forming a second amorphous silicon thin film on a first surface of the polycrystalline silicon thin film; and etching until the second amorphous silicon thin film is completely removed toward a direction of the polycrystalline silicon thin film from the second amorphous silicon thin film by applying a dry etching process. The present disclosure further discloses a manufacturing method of a thin film transistor array substrate which includes the steps of manufacturing an active layer: forming a layer of a polycrystalline silicon thin film according to the previous polycrystalline silicon thin film; and etching the polycrystalline silicon thin film to form a patterned active layer.

公开(公告)号：US20180350925A1

公开(公告)日：2018-12-06

申请号：US16100353

申请日：2018-08-10

Applicant: International Business Machines Corporation

Inventor： Lukas Czornomaz ,  Veeresh V. Deshpande ,  Vladimir Djara

IPC: H01L29/417

CPC classification number: H01L29/41783 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66522 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/786

Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

公开(公告)号：US20180277380A1

公开(公告)日：2018-09-27

申请号：US15751699

申请日：2017-03-10

Applicant: TOHO ENGINEERING CO., LTD.

Inventor： Tatsutoshi SUZUKI ,  Eisuke SUZUKI ,  Daisuke SUZUKI

IPC: H01L21/306 ,  B24B37/07 ,  B24B1/04 ,  B24B37/34 ,  H01L21/321

CPC classification number: H01L21/30625 ,  B24B1/00 ,  B24B1/04 ,  B24B37/07 ,  B24B37/34 ,  B24B41/007 ,  H01L21/306 ,  H01L21/32115

Abstract: A planarization processing device for polishing a substrate, e.g., a semiconductor wafer, includes two planarization processing sections (SP1, SP2) that each include a holder (62) for holding a workpiece (W), a drive motor (71) that rotates the holder (62), a support plate (4) holds a pad (5), a linear guide (3) that guides reciprocal movement of the support plate (4) in a direction parallel to the surface of the pad (5), and a drive cylinder (72) that advances the holder (62) or the support plate (4) in a direction that intersects the surface of the workpiece W or the pad (5) to cause the opposing surfaces of the workpiece and the pad (5) to be at least proximal to each other. A primary driver (PD) causes the support plates (4) of the planarization processing sections (SP1, SP2) to reciprocate along the same straight line in opposite phases.

公开(公告)号：US10068803B2

公开(公告)日：2018-09-04

申请号：US14722597

申请日：2015-05-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Jun Luo ,  Chunlong Li ,  Jian Deng ,  Chao Zhao

IPC: H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/321 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31105 ,  H01L21/32115 ,  H01L21/32132 ,  H01L21/76229 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/1083 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7848

Abstract: A planarization process is disclosed. The method includes forming a trench in an area of a material layer which has a relatively high loading condition for sputtering. The method further includes sputtering the material layer to make the material layer flat.