公开(公告)号：US07567892B2

公开(公告)日：2009-07-28

申请号：US10284294

申请日：2002-10-31

申请人： Geoff Barrett ,  Simon Christopher Dequin Clemow ,  Andrew Jon Dawson

发明人： Geoff Barrett ,  Simon Christopher Dequin Clemow ,  Andrew Jon Dawson

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Techniques directed to realizing and verifying a logic model design are provided by first dividing the logic model design into two or more logic portions. The various model portions can then realized to form various realized logic portions. A first realized logic portion can then be wrapped and formally verified against its respective model. The wrapper can then be verified by first applying the wrapper to a second logic model portion and a second realized logic portion, then formally verifying them against each other. The resulting output can then be used to prove wrapper correctness.

摘要翻译： 通过首先将逻辑模型设计划分为两个或多个逻辑部分来提供用于实现和验证逻辑模型设计的技术。 然后可以实现各种模型部分以形成各种实现的逻辑部分。 然后可以根据其相应的模型包装和正式验证第一个实现的逻辑部分。 然后可以通过首先将包装器应用于第二逻辑模型部分和第二实现的逻辑部分，然后正确地验证它们来验证包装器。 所得到的输出可用于证明封装的正确性。

公开(公告)号：US20050060577A1

公开(公告)日：2005-03-17

申请号：US10664055

申请日：2003-09-17

申请人： Geoff Barrett ,  Richard Porter

发明人： Geoff Barrett ,  Richard Porter

IPC分类号： G06F9/30 ,  G06F9/315 ,  G06F9/318 ,  G06F9/38 ,  H04L9/00 ,  H04L9/32

CPC分类号： G06F9/3836 ,  G06F9/30032 ,  G06F9/327 ,  G06F9/328 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885

摘要： The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt requests or interrupt pseudo-instructions communicatively coupled to the processor. The method comprises the steps of processing at least one actual instruction in the processor in an instruction pipeline, and if an external interrupt request is received by the processor, the actual instruction is replaced with the pseudo-instruction. Pursuant to the method, instructions are concurrently processed in the processor in an instruction pipeline with several stages. In the instruction pipeline, instructions are processed by an instruction fetch stage, an instruction decode stage, an instruction issue stage, an execute stage and a result write-back stage. Thereby, interrupt requests are only processed at the fetch stage of the instruction pipeline. The device of an interrupt support mechanism and the method for operating said device provides the advantage a simplification of interrupt verification.

摘要翻译： 本发明涉及一种用于中断验证支持机制的装置和用于操作所述装置的方法，该装置包括处理器和用于通信地耦合到处理器的外部中断请求或中断伪指令的输入。 该方法包括以下步骤：在指令流水线中处理处理器中的至少一个实际指令，如果处理器接收到外部中断请求，则用伪指令替换实际指令。 根据该方法，在具有多个级的指令流水线中，在处理器中同时处理指令。 在指令流水线中，通过指令提取阶段，指令解码阶段，指令发布阶段，执行阶段和结果回写阶段来处理指令。 因此，中断请求仅在指令流水线的提取阶段处理。 中断支持机制的装置和操作所述装置的方法提供了简化中断验证的优点。

公开(公告)号：US06816821B1

公开(公告)日：2004-11-09

申请号：US09477790

申请日：1999-12-31

申请人： Geoff Barrett

发明人： Geoff Barrett

IPC分类号： G06F1710

CPC分类号： G06F17/504

摘要： A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system. The processing system comprises a logical device for transforming the transition functions of the system into constraints on the reverse model, and a parameterization processor for applying a parameterization of the constraints to the estimate of transition functions of reverse system to form transition functions of the

公开(公告)号：US07640151B2

公开(公告)日：2009-12-29

申请号：US10812103

申请日：2004-03-30

申请人： Simon Smith ,  Geoff Barrett ,  Martin Vickers

发明人： Simon Smith ,  Geoff Barrett ,  Martin Vickers

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

摘要翻译： 提供了一种用于模拟电子电路的方法和系统，该电路由多个逻辑元件的网络表示，该电路包括第一和第二异步时钟域，由此将抖动元件另外插入在电路边界的预定部分 第一和第二时钟域，抖动元件被表示为逻辑元件，其值是随机设置的。

公开(公告)号：US6134512A

公开(公告)日：2000-10-17

申请号：US979450

申请日：1997-11-24

申请人： Geoff Barrett

发明人： Geoff Barrett

IPC分类号： G06F19/00 ,  G06F17/50 ,  G06G7/62

CPC分类号： G06F17/504

摘要： A system for representing a physical environment comprises a first store for holding a set of state bits, a second store for holding a set of input bits, an input device for inputting a set of initial states of said state bits into said first store, means for implementing a set of state transition functions for manipulating said input bits and said state bits, and means for generating input bits satisfying a set of constrains representing restrictions on the physical environment.

摘要翻译： 用于表示物理环境的系统包括用于保存一组状态位的第一存储器，用于保存一组输入位的第二存储器，用于将所述状态位的一组初始状态输入到所述第一存储器中的输入装置， 用于实现用于操纵所述输入比特和所述状态比特的一组状态转换功能，以及用于生成满足表示对所述物理环境的限制的一组约束的输入比特的装置。

公开(公告)号：US07765388B2

公开(公告)日：2010-07-27

申请号：US10664055

申请日：2003-09-17

申请人： Geoff Barrett ,  Richard Porter

发明人： Geoff Barrett ,  Richard Porter

IPC分类号： G06F9/00 ,  G06F9/44

CPC分类号： G06F9/3836 ,  G06F9/30032 ,  G06F9/327 ,  G06F9/328 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3885

摘要： The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt requests or interrupt pseudo-instructions communicatively coupled to the processor. The method comprises the steps of processing at least one actual instruction in the processor in an instruction pipeline, and if an external interrupt request is received by the processor, the actual instruction is replaced with the pseudo-instruction. Pursuant to the method, instructions are concurrently processed in the processor in an instruction pipeline with several stages. In the instruction pipeline, instructions are processed by an instruction fetch stage, an instruction decode stage, an instruction issue stage, an execute stage and a result write-back stage. Thereby, interrupt requests are only processed at the fetch stage of the instruction pipeline. The device of an interrupt support mechanism and the method for operating said device provides the advantage a simplification of interrupt verification.

摘要翻译： 本发明涉及一种用于中断验证支持机制的装置和用于操作所述装置的方法，该装置包括处理器和用于通信地耦合到处理器的外部中断请求或中断伪指令的输入。 该方法包括以下步骤：在指令流水线中处理处理器中的至少一个实际指令，如果处理器接收到外部中断请求，则用伪指令替换实际指令。 根据该方法，在具有多个级的指令流水线中，在处理器中同时处理指令。 在指令流水线中，通过指令提取阶段，指令解码阶段，指令发布阶段，执行阶段和结果回写阶段来处理指令。 因此，中断请求仅在指令流水线的提取阶段处理。 中断支持机制的装置和操作所述装置的方法提供了简化中断验证的优点。

公开(公告)号：US07149663B1

公开(公告)日：2006-12-12

申请号：US09159748

申请日：1998-09-23

申请人： Geoff Barrett

发明人： Geoff Barrett

IPC分类号： G06F7/60 ,  G06F17/50 ,  G06F9/06

CPC分类号： G06F17/504

摘要： A method for selecting an order in which to sift variables in a binary decision diagram. The method includes an act of arranging the variables of the binary decision diagram on nodes of a graph, with the nodes of the graph being labeled with the variables of the system such that a set of functions labeling the leaves reachable from a node correspond to the set of functions which depend on the variables labeling the node. The method further includes an act of traversing the graph in a depth first manner to produce a list of the labels in the selected order.

摘要翻译： 一种用于选择在二进制决策图中筛选变量的顺序的方法。 该方法包括将二进制决策图的变量布置在图的节点上的动作，其中图形的节点用系统的变量标记，使得标记可从节点到达的叶片的一组函数对应于 一组功能取决于标记节点的变量。 该方法还包括以深度第一方式遍历图的动作以产生所选择的顺序中的标签的列表。

公开(公告)号：US6031983A

公开(公告)日：2000-02-29

申请号：US28415

申请日：1998-02-24

申请人： Geoff Barrett

发明人： Geoff Barrett

IPC分类号： G06F19/00 ,  G06F17/50 ,  G06F17/11

CPC分类号： G06F17/504

摘要： A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system. The processing system comprises a logical device for transforming the transition functions of the system into constraints on the reverse model, and a parameterization processor for applying a parameterization of the constraints to the estimate of transition functions of reverse system to form transition functions of the reverse model.

摘要翻译： 用于合成系统的反向模型的装置包括存储表示系统的转换功能的位的第一存储器，存储表示反向模型的转换功能的估计的位的第二存储器和处理系统。 处理系统包括用于将系统的过渡功能转换为反向模型的约束的逻辑设备，以及参数化处理器，用于将约束的参数化应用于反向系统的转换函数的估计，以形成反向模型的转换函数 。

公开(公告)号：US07143073B2

公开(公告)日：2006-11-28

申请号：US10115011

申请日：2002-04-04

申请人： Geoff Barrett

发明人： Geoff Barrett

IPC分类号： G06F15/18

CPC分类号： G06F11/263 ,  G06F11/2236

摘要： The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of states 2 and transitions 4 determined by weights W1, W2 . . . W10 is used to generate a sequence of instructions. The weights determine the next state as well as an instruction and operands for each state. The weights may be adapted based on the generated sequence and further sequences are generated.

摘要翻译： 本发明涉及生成用于测试处理器的操作的指令测试套件。 具有由权重W 1，W 2确定的多个状态2和转换4的模糊有限状态机。 。 。 W 10用于产生指令序列。 权重确定下一个状态以及每个状态的指令和操作数。 可以基于生成的序列来调整权重，并且生成另外的序列。

公开(公告)号：US20050222832A1

公开(公告)日：2005-10-06

申请号：US10812103

申请日：2004-03-30

申请人： Simon Smith ,  Geoff Barrett ,  Martin Vickers

发明人： Simon Smith ,  Geoff Barrett ,  Martin Vickers

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.

摘要翻译： 提供了一种用于模拟电子电路的方法和系统，该电路由多个逻辑元件的网络表示，该电路包括第一和第二异步时钟域，由此将抖动元件另外插入在电路边界的预定部分 第一和第二时钟域，抖动元件被表示为逻辑元件，其值是随机设置的。