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公开(公告)号：US07948060B2
公开(公告)日：2011-05-24
申请号：US12165776
申请日：2008-07-01
IPC分类号： H01L23/544
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit and corresponding method of manufacture. The integrated circuit has a die comprising: an outer strengthening ring around a periphery of the die, the outer ring having one or more gaps; and an inner strengthening ring within the outer ring and around interior circuitry of the die, the inner ring having one or more gaps offset from the gaps of the outer ring. One or more conducting members are electrically isolated from said rings and electrically connected to the interior circuitry, each member passing through a gap of the inner ring and through a gap of the outer ring.
摘要翻译： 一种集成电路及相应的制造方法。 所述集成电路具有模具，所述模具包括：围绕所述模具的周边的外部加强环，所述外部环具有一个或多个间隙; 以及在所述外环内和所述模具的内部电路周围的内加强环，所述内环具有从所述外环的间隙偏移的一个或多个间隙。 一个或多个导电构件与所述环电隔离并电连接到内部电路，每个构件穿过内环的间隙并通过外环的间隙。
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公开(公告)号：US20100001405A1
公开(公告)日：2010-01-07
申请号：US12165776
申请日：2008-07-01
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit and corresponding method of manufacture. The integrated circuit has a die comprising: an outer strengthening ring around a periphery of the die, the outer ring having one or more gaps; and an inner strengthening ring within the outer ring and around interior circuitry of the die, the inner ring having one or more gaps offset from the gaps of the outer ring. One or more conducting members are electrically isolated from said rings and electrically connected to the interior circuitry, each member passing through a gap of the inner ring and through a gap of the outer ring.
摘要翻译： 一种集成电路及相应的制造方法。 所述集成电路具有模具，所述模具包括：围绕所述模具的周边的外部加强环，所述外部环具有一个或多个间隙; 以及在所述外环内和所述模具的内部电路周围的内加强环，所述内环具有从所述外环的间隙偏移的一个或多个间隙。 一个或多个导电构件与所述环电隔离并电连接到内部电路，每个构件穿过内环的间隙并通过外环的间隙。
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公开(公告)号：US06766503B2
公开(公告)日：2004-07-20
申请号：US10158000
申请日：2002-05-31
IPC分类号： G06F1750
CPC分类号： G06F17/5077 , G06F17/5068 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing. The protective routing also bridges the at least one port to inter-block routing connected to the net in a halo region. Software and/or a computer program product that can be used for multi-layer circuit design is also described.
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公开(公告)号：US07567892B2
公开(公告)日：2009-07-28
申请号：US10284294
申请日：2002-10-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Techniques directed to realizing and verifying a logic model design are provided by first dividing the logic model design into two or more logic portions. The various model portions can then realized to form various realized logic portions. A first realized logic portion can then be wrapped and formally verified against its respective model. The wrapper can then be verified by first applying the wrapper to a second logic model portion and a second realized logic portion, then formally verifying them against each other. The resulting output can then be used to prove wrapper correctness.
摘要翻译： 通过首先将逻辑模型设计划分为两个或多个逻辑部分来提供用于实现和验证逻辑模型设计的技术。 然后可以实现各种模型部分以形成各种实现的逻辑部分。 然后可以根据其相应的模型包装和正式验证第一个实现的逻辑部分。 然后可以通过首先将包装器应用于第二逻辑模型部分和第二实现的逻辑部分，然后正确地验证它们来验证包装器。 所得到的输出可用于证明封装的正确性。
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公开(公告)号：US07100138B2
公开(公告)日：2006-08-29
申请号：US10863333
申请日：2004-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing. The protective routing also bridges the at least one port to inter-block routing connected to the net in a halo region. Software and/or a computer program product that can be used for multi-layer circuit design is also described.
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