公开(公告)号：US4354124A

公开(公告)日：1982-10-12

申请号：US158310

申请日：1980-06-10

申请人： Takeshi Shima ,  Ken-ichi Torii

发明人： Takeshi Shima ,  Ken-ichi Torii

IPC分类号： H03K5/26 ,  G01R25/00 ,  H03D13/00 ,  H03K13/32

CPC分类号： G01R25/00 ,  G01R25/005 ,  H03D13/004

摘要： A digital phase comparator circuit comprises a digital phase comparator having output terminals and a circuit connected to the output terminals of the phase comparator and arranged to remove undesired pulse output signals simultaneously appearing at the output terminals due to propagation delay times of logic gates incorporated in the phase comparator.

摘要翻译： 数字相位比较器电路包括具有输出端和数字相位比较器的数字相位比较器，该电路连接到相位比较器的输出端并且被布置成由于并入在输入端的逻辑门的传播延迟时间而消除同时出现在输出端的不需要的脉冲输出信号 相位比较器。

公开(公告)号：US4315165A

公开(公告)日：1982-02-09

申请号：US94987

申请日：1979-11-16

申请人： Shyoichi Shimizu ,  Ken-Ichi Torii

发明人： Shyoichi Shimizu ,  Ken-Ichi Torii

IPC分类号： H03K3/286 ,  H03K3/289 ,  H03K21/00 ,  H03K23/00 ,  H03K23/08

CPC分类号： H03K3/289

摘要： Disclosed is a frequency divider which includes a master flip-flop, transfer gate transistors for the master flip-flop, a slave flip-flop, transfer gate transistors for the slave flip-flop, and switching transistors to energize one of the master slave flip-flops in response to an input signal. Among transistors constituting the flip-flops and the transfer gate transistors in this frequency divider, each double-collector transistor serves as two transistors having base and emitter in common.

摘要翻译： 公开了一种分频器，其包括主触发器，用于主触发器的传输门晶体管，从触发器，用于从触发器的传输栅晶体管，以及用于为主从触发器中的一个供电的开关晶体管 - 响应于输入信号的跳跃。 在该分频器中构成触发器的晶体管和传输栅极晶体管中，每个双集电极晶体管用作具有基极和发射极共同的两个晶体管。

公开(公告)号：US4271531A

公开(公告)日：1981-06-02

申请号：US48984

申请日：1979-06-15

申请人： Ken-Ichi Torii ,  Takeshi Shima

发明人： Ken-Ichi Torii ,  Takeshi Shima

IPC分类号： H03L7/18 ,  H01Q1/42 ,  H03J5/02 ,  H03L7/06 ,  H03L7/197 ,  H04B1/16

CPC分类号： H03J5/0281 ,  H03L7/06 ,  H03L7/1974

摘要： In a frequency synthesizer with phase-locked loop in which the output signal from a voltage controlled oscillator is frequency-divided by a variable frequency dividing circuit and the frequency-divided one, together with a reference frequency signal, is applied to a phase comparator and the output signal from the phase comparator is fed back to the voltage control oscillator, the variable frequency dividing circuit is comprised of a first variable frequency divider for frequency-dividing the frequency of the output signal from the voltage controlled oscillator into a 1/K frequency, a second variable frequency divider for frequency-dividing the frequency of the output signal from the first variable frequency divider into a 1/m frequency, and a rate multiplier which receives the output signal from the second variable frequency divider to produce Q pulses (Q is an integer between 0 to P-1 where P is an integer) when receiving P input pulses, and to change the frequency dividing ratio K of the first variable frequency divider.

摘要翻译： 在具有锁相环的频率合成器中，来自压控振荡器的输出信号被可变分频电路分频，并且分频后的频率合成器与参考频率信号一起施加到相位比较器， 来自相位比较器的输出信号被反馈到压控振荡器，可变分频电路由用于将来自压控振荡器的输出信号的频率分频为1 / K频率的第一可变分频器 ，第二可变分频器，用于将来自第一可变分频器的输出信号的频率分频为1 / m频率;以及速率倍增器，其接收来自第二可变分频器的输出信号以产生Q个脉冲（Q 是0〜P-1之间的整数，其中P是整数）当接收到P个输入脉冲时，并且改变分频比K 第一个可变分频器。