Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array
    2.
    发明授权
    Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array 失效
    从无边界门阵列制造各种大小的钝化集成电路芯片的方法

    公开(公告)号:US06316334B1

    公开(公告)日:2001-11-13

    申请号:US09642394

    申请日:2000-08-18

    IPC分类号: H01L21301

    摘要: Effective passivation structures and guard rings can be formed in borderless gate arrays by forming the gates in an array of discrete blocks separated by thin scribe lines in which the substrate is not covered by gates. Diffusions for guard rings can be formed in the substrate for guard ring purposes, and passivation structures can be sealingly attached to the substrate. Various circuit metalizations such as discrete layers or different circuits can be produced with a single mask by covering all but a selected portion of the mask during exposure.

    摘要翻译: 通过在薄的划痕线分隔的离散块的阵列中形成栅极,可以在无边界门阵列中形成有效的钝化结构和保护环,其中衬底不被栅极覆盖。 保护环的扩散可以形成在衬底中用于保护环目的,并且钝化结构可以密封地附着到衬底上。 通过在曝光期间覆盖掩模的所有部分以外,可以通过单个掩模来生产各种电路金属化,例如离散层或不同的电路。

    High speed analog-to-digital converter
    3.
    发明授权
    High speed analog-to-digital converter 失效
    高速模数转换器

    公开(公告)号:US06433725B1

    公开(公告)日:2002-08-13

    申请号:US09722917

    申请日:2000-11-27

    IPC分类号: H03M112

    CPC分类号: H03M7/165 H03M1/36

    摘要: A method of converting a thermometer code in an analog-to-digital converter to a binary code. The method involves counting the ones in the thermometer code and using the parity of the count as bit 0 of the binary code; downsampling the thermometer code by dropping every other bit to form a downsampled code; counting the ones in the downsampled code, and using the parity of that count as bit 1 of the binary code; and repeating the procedure until the binary code is completed. A circuit carrying out this method in a single clock cycle without computations is disclosed.

    摘要翻译: 一种将模拟 - 数字转换器中的温度计代码转换为二进制代码的方法。 该方法涉及对温度计代码中的计数,并将计数的奇偶校验作为二进制代码的位0; 通过丢弃每隔一个位来对温度计代码进行下采样,形成一个下采样代码; 对下采样码中的码进行计数,并使用该计数的奇偶校验作为二进制码的位1; 并重复该过程直到二进制代码完成。 公开了在没有计算的情况下在单个时钟周期中执行该方法的电路。

    Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array
    4.
    发明授权
    Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array 失效
    从无边界门阵列制造各种大小的钝化集成电路芯片的方法

    公开(公告)号:US06373122B1

    公开(公告)日:2002-04-16

    申请号:US09290495

    申请日:1999-04-12

    IPC分类号: H01L23544

    摘要: Effective passivation structures and guard rings can be formed in borderless gate arrays by forming the gates in an array of discrete blocks separated by thin scribe lines in which the substrate is not covered by gates. Diffusions for guard rings can be formed in the substrate for guard ring purposes, and passivation structures can be sealingly attached to the substrate. Various circuit metalizations such as discrete layers or different circuits can be produced with a single mask by covering all but a selected portion of the mask during exposure.

    摘要翻译: 通过在薄的划痕线分隔的离散块的阵列中形成栅极,可以在无边界门阵列中形成有效的钝化结构和保护环,其中衬底不被栅极覆盖。 保护环的扩散可以形成在衬底中用于保护环目的,并且钝化结构可以密封地附着到衬底上。 通过在曝光期间覆盖掩模的所有部分以外,可以通过单个掩模来生产各种电路金属化,例如离散层或不同的电路。